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copyright ? cirrus logic, inc. 2008 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 10-in, 6-out, 2 vrms audio codec d/a features ? dual 24-bit stereo dacs ? multi-bit delta-sigma modulator ? 100 db dynamic range (a-wtd) ? -90 db thd+n ? integrated line driver ? 2 vrms output ? single-ended outputs ? up to 96 khz sampling rates ? stereo 7:1 output multiplexer ? volume control with soft ramp ? 0.5 db step size ? zero crossing click-free transitions ? selectable serial audio interface formats ? left- or right-justified, up to 24-bit ? i2s up to 24-bit ? selectable 50/15 s de-emphasis ? internal analog mute ? control output for external muting ? popguard ? technology a/d features ? multi-bit delta-sigma modulator ? 24-bit conversion ? up to 96 khz sampling rates ? 95 db dynamic range (a-wtd) ? -88 db thd+n ? stereo 5:1 input multiplexer ? digital volume control with soft ramp ? 0.5 db step size ? selectable serial audio interface formats ? left-justified ?i2s ? high-pass filter or dc offset calibration see system features , general description , and order- ing information on page 2 . 1.8 v to 3.3 v internal voltage reference multibit ? modulator multibit ? modulator stereo dac multibit oversampling stereo adc low-latency decimation filter stereo input 1 serial audio inputs serial audio output 3.3 v 3.3 v 5:1 mux 7:1 mux volume control/mixer volume control/mixer pcm serial interface mute control register configuration level translator level translator level translator reset spi & i 2 c control data mute 1 mute 2 mute 3 stereo input 2 stereo input 3 stereo input 4 stereo input 5 interrupt adc overflow 7:1 mux 7:1 mux stereo output 1 stereo output 2 stereo output 3 9 v to12 v pcm serial interface mute mute mute volume control/high pass filter 5 5 5 stereo dac january '08 ds721a6 cs42324
2 ds721a6 cs42324 system features ? direct interface with 1.8 v to 3.3 v logic levels ? supports asynchronous serial port operation ? two independent clock domains ? adc, dac1, and dac2 can be independently assigned to the two clock domains ? each serial port supports master or slave operation ? internal digital loopback ? +3.3 v analog power supply ? +3.3 v digital power supply ? +9 v to +12 v high-voltage power supply ? hardware or software mode configuration ? supports i2c ? and spi ? software interface general description the cs42324 is a highly integrated stereo audio codec. the cs42324 perf orms stereo analog-to- digital (a/d) and up to four channels of digital-to-analog (d/a) conversion of up to 24-bit serial values at sample rates up to 96 khz. a 5:1 stereo input multiplexe r is included for selecting between line-level inputs. the output of the input multi- plexer is followed by an advanced 3rd-order, multi-bit delta-sigma modulator and digital filtering/decimation. sampled data is transmitted by the serial audio inter- face at rates from 4 khz to 96 khz, in either slave or master mode. the d/a converter is based on a 5th-order multi-bit del- ta-sigma modulator with an ultra-linear low-pass filter and offers a volume control that operates with a 0.5 db step size. it incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops. an integrated 7:1 stereo output multiplexer on each of the three stereo 2 vrms line-level outputs is used to se- lect any of the 5 stereo analog inputs, for analog bypass support, or the outputs of the 2 internal dacs. each 2 vrms output can be muted with the selectable analog mute function. standard 50/15 s de-emphasis is available for a 44.1 khz sample rate for co mpatibility with digital audio programs mastered using the 50/15 s pre-emphasis technique. integrated digital level translators allow easy interfacing between the cs42324 and other devices operating over a wide range of logic levels. the cs42324 is available in a 48-pin lqfp package in commercial (-40c to +85c) and automotive (-40c to +105c) grades. the cdb42324 customer demonstra- tion board is also available for device evaluation and implementation suggestions. please refer to ?ordering information? on page 71 for complete details.
ds721a6 3 cs42324 table of contents 1. pin descriptions ........................................................................................................... ................... 8 1.1 software mode ............................................................................................................. .................... 8 1.2 hardware mode .............. ............................................................................................... ................. 10 1.3 digital i/o pin characteristics ........................................................................................... .............. 12 2. characteristics and specificatio ns .......... ................. ................ ................ ................ ......... 13 recommended operating conditions ................................................................................... 13 absolute maximum ratings ...................................................................................................... .13 dac analog characteristics - commercial (-cqz) ........................................................... 14 dac analog characteristics - automotive (-dqz) ............................................................ 15 dac combined interpolation & on-chip anal og filter response .. ................ ............ 16 adc analog characteristics - commercial (-cqz) ........................................................... 17 adc analog characteristics - automotive (-dqz) ............................................................ 18 adc digital filter characteristics ....................................................................................... 19 analog pass-thru characteristics ................ ................ ................ ................ ............. ......... 20 dc electrical characteristics .............................................................................................. 21 digital interface characteristics ....................................................................................... 21 switching characteristics - serial audio .......................................................................... 22 switching characteristics - serial audio (cont.) ........................................................... 23 switching characteristics - software mode - i2c format ........................................... 24 switching characteristics - software mode - spi format .......................................... 25 3. typical connection diagrams ................................................................................................ .26 4. applications ............................................................................................................... .................... 28 4.1 system clocking ........................................................................................................... .................. 28 4.1.1 master clock ............................................................................................................ ............. 28 4.1.2 synchronous / asynchronous mode ................ ...................................................................... 29 4.2 serial port operation ..................................................................................................... ................. 29 4.2.1 master mode ............................................................................................................. ............ 30 4.2.2 slave mode .............................................................................................................. ............. 30 4.2.3 adc, dac1, and dac2 clock selection ................................................................................ 31 4.2.4 high-impedance digital output ........................................................................................... .. 31 4.2.5 digital interface formats ............................................................................................... ........ 32 4.2.6 synchronization of multiple devices ..................................................................................... .32 4.3 analog-to-digital data path ............................................................................................... ............. 33 4.3.1 adc analog input multiplexer ............................................................................................ ... 33 4.3.2 adc description ......................................................................................................... ........... 33 4.3.3 high-pass filter and dc offset calibration ........................................................................... 34 4.3.4 digital attenuation control ............................................................................................. ........ 34 4.4 digital-to-analog data path ............................................................................................... ............. 34 4.4.1 digital volume control .................................................................................................. ......... 34 4.4.2 mono channel mixer ...................................................................................................... ....... 34 4.4.3 de-emphasis filter ...................................................................................................... .......... 35 4.4.4 internal digital loopback ............................................................................................... ........ 35 4.4.5 dac description ......................................................................................................... ........... 35 4.4.6 analog output multiplexer ............................................................................................... ...... 36 4.4.7 output transient control ................................................................................................ ....... 36 4.4.8 mute control ............................................................................................................ .............. 37 4.5 initialization ............................................................................................................ ......................... 37 4.5.1 determining hardware or software mode ............................................................................. 37 4.5.2 hardware mode st art-up .................................................................................................. .... 37 4.5.3 software mode start-up .................................................................................................. ...... 38 4.5.4 initialization flow chart ...................... ......................................................................... .......... 39 4.6 device control ............................................................................................................ .................... 40
4 ds721a6 cs42324 4.6.1 hardware mode ........................................................................................................... .......... 40 4.6.2 software mode - i2c control port ............. ........................................................................... .. 41 4.6.3 software mode - spi contro l port ........................................................................................ .42 4.6.4 memory address pointer (m ap) ............................................................................................ 43 4.7 interrupts and overflow ................................................................................................... ............... 43 5. register quick reference ................................................................................................... ..... 44 6. register description ....................................................................................................... ........... 46 6.1 device i.d. and revision register (address 0 0h) (read only) ...................................................... 46 6.1.1 device i.d. (read only) ................................................................................................. ....... 46 6.1.2 chip revision (read only) ............................................................................................... ..... 46 6.2 mute control (address 01h) ................................................................................................ ........... 46 6.2.1 system mclk source ...................................................................................................... ..... 46 6.2.2 mute dac2 left-channel ......................... ......................................................................... .... 46 6.2.3 mute dac2 right-channel ................................................................................................. ... 47 6.2.4 mute dac1 left-channel ......................... ......................................................................... .... 47 6.2.5 mute dac1 right-channel ................................................................................................. ... 47 6.2.6 mute adc left-channel ................................................................................................... ..... 47 6.2.7 mute adc right-channel .................................................................................................. .... 47 6.3 operational control (a ddress 02h) ......................................................................................... ........ 47 6.3.1 global power-down ....... ................................................................................................ ....... 47 6.3.2 int pin high/low active (int_h/l) ....................................................................................... 48 6.3.3 freeze .................................................................................................................. ................. 48 6.3.4 tri-state sdout ......................................................................................................... .......... 48 6.3.5 tri-state serial port 1 ................................................................................................. ........... 48 6.3.6 tri-state serial port 2 ................................................................................................. ........... 49 6.4 serial port 1 control (address 03h) ....................................................................................... ......... 49 6.4.1 serial port 1 master/slave select .......... ............................................................................. ... 49 6.4.2 serial port 1 speed mode ................................................................................................ ..... 49 6.4.3 mclk1 divider ........................................................................................................... ........... 49 6.4.4 serial port 1 mclk source ............................................................................................... ..... 49 6.5 serial port 2 control (address 04h) ....................................................................................... ......... 50 6.5.1 serial port 2 master/slave select .......... ............................................................................. ... 50 6.5.2 serial port 2 speed mode ................................................................................................ ..... 50 6.5.3 mclk2 divider ........................................................................................................... ........... 50 6.5.4 serial port 2 mclk source ............................................................................................... .... 50 6.6 adc clocking (address 06h) ................................................................................................ .......... 50 6.6.1 adc mclk source ......................................................................................................... ...... 50 6.6.2 adc serial port source .................................................................................................. ....... 51 6.6.3 adc digital interface format (adc_dif) .............................................................................. 51 6.7 dac1 clocking (address 07h) ............................................................................................... ......... 51 6.7.1 dac1 mclk source ........................................................................................................ ..... 51 6.7.2 dac1 serial port source ................................................................................................. ...... 51 6.7.3 dac1 digital interface format (dac1_dif) .......................................................................... 51 6.8 dac2 clocking (address 08h) ............................................................................................... ......... 52 6.8.1 dac2 mclk source ........................................................................................................ ..... 52 6.8.2 dac2 serial port source ................................................................................................. ...... 52 6.8.3 dac2 digital interface format (dac2_dif) .......................................................................... 52 6.9 adc control (address 0ah) ................................................................................................. .......... 52 6.9.1 adc high-pass filter freeze ............................................................................................. ... 52 6.9.2 adc soft ramp control ................................................................................................... ..... 52 6.9.3 analog input selection .................................................................................................. ........ 53 6.10 dac1 control (address 0bh) ............................................................................................... ........ 53 6.10.1 dac1 de-emphasi s control ............................................................................................... .53 6.10.2 dac1 single volume cont rol ............................................................................................. .53
ds721a6 5 cs42324 6.10.3 dac1 soft ramp control ................................................................................................. ... 53 6.10.4 dac1 zero cross control ...................... .......................................................................... ... 54 6.10.5 dac1 loop-back ......................................................................................................... ........ 54 6.10.6 dac1 invert signal polarity ............................................................................................ ..... 54 6.10.7 dac1 channel mixer ..................................................................................................... ...... 54 6.11 dac2 control (address 0ch) ............................................................................................... ........ 55 6.11.1 dac2 de-emphasis control ............................................................................................... .55 6.11.2 dac2 single volume control ............................................................................................. .55 6.11.3 dac2 soft ramp control ................................................................................................. ... 55 6.11.4 dac2 zero cross control ...................... .......................................................................... ... 55 6.11.5 dac2 loop-back ......................................................................................................... ........ 56 6.11.6 dac2 invert signal polarity ............................................................................................ ..... 56 6.11.7 dac2 channel mixer ..................................................................................................... ...... 56 6.12 aout1 control (address 0dh) .............................................................................................. ....... 56 6.12.1 external mute control pin .............................................................................................. ..... 56 6.12.2 aout1 select ........................................................................................................... .......... 56 6.13 aout2 control (address 0eh) .............................................................................................. ....... 57 6.13.1 external mute control pin .............................................................................................. ..... 57 6.13.2 aout2 select ........................................................................................................... .......... 57 6.14 aout3 control (address 0fh) .............................................................................................. ....... 57 6.14.1 external mute control pin .............................................................................................. ..... 57 6.14.2 aout3 select ........................................................................................................... .......... 58 6.15 adcx volume control: adca (address 10h) & adcb (address 11h) ......................................... 58 6.16 dac1x volume control: dac1a (address 12h) & dac1b (address 13h) ................................... 58 6.17 dac2x volume control: dac1a (address 14h) & dac1b (address 15h) ................................... 59 6.18 interrupt mode (address 16h) ................ ............................................................................. .......... 59 6.19 interrupt mask (address 17h) ............................................................................................. .......... 59 6.19.1 dac2 auto mute left mask (dac2_amute lm) ................................................................ 60 6.19.2 dac2 auto mute right mask (dac2_amute rm) ............................................................. 60 6.19.3 dac1 auto mute left mask (dac1_amute lm) ................................................................ 60 6.19.4 dac1 auto mute right mask (dac1_amute lm) .............................................................. 60 6.19.5 serial port 2 clock error mask (sp2_cl kerrm) .............................................................. 60 6.19.6 serial port 1 clock error mask (sp1_cl kerrm) .............................................................. 60 6.19.7 adc positive overflow mask (adc_ovflpm ) ................................................................... 61 6.19.8 adc negative overflow mask (adc_ovflnm ) ................................................................. 61 6.20 interrupt status (address 18h) (read only) ............................................................................... .. 61 6.20.1 dac2 auto mute left in terrupt status (dac2_amutel) ................................................... 61 6.20.2 dac2 auto mute right in terrupt status (dac2_amuter) ................................................ 61 6.20.3 dac1 auto mute left in terrupt status (dac1_amutel) ................................................... 62 6.20.4 dac1 auto mute right in terrupt status (dac1_amutel) . ................................................ 62 6.20.5 serial port 2 clock error interrupt status (sp2_clkerr) . ................................................ 62 6.20.6 serial port 1 clock error interrupt status (sp1_clkerr) . ................................................ 62 6.20.7 adc positive overflow interrupt bit (adc_ ovflp) ............................................................ 62 6.20.8 adc negative overflow in terrupt bit (adc_ovfln) .......................................................... 63 7. grounding and power supply decoupling ........................................................................ 64 8. adc filter plots .......................................................................................................... ................. 65 9. dac digital filter response plots ................................................................................ 67 10. parameter definitions ..................................................................................................... ......... 69 11. package dimensions ....................................................................................................... .......... 70 thermal characteristics and specifications ................................................................. 70 12. ordering information ...................................................................................................... ........ 71 13. revision history .......................................................................................................... ................ 71
6 ds721a6 cs42324 list of figures figure 1.equivalent analog output load ........................................................................................ .......... 16 figure 2.maximum analog output loading ............ ............................................................................ ....... 16 figure 3.serial input timing .................................................................................................. .................... 22 figure 4.serial output timing ................................................................................................. .................. 23 figure 5.software mode timing - i2c format .................................................................................... ........ 24 figure 6.software mode timing - spi mode ...... ................................................................................ ....... 25 figure 7.typical connection diagram - software mode ........................................................................... 26 figure 8.typical connection diagram - hardware mo de .......................................................................... 2 7 figure 9.serial port topology ................................................................................................. .................. 29 figure 10.master mode clock generation ........................................................................................ ........ 30 figure 11.converter clocking .................................................................................................. ................. 31 figure 12.tri-state serial po rt ............................................................................................... ................... 31 figure 13.left-justified up to 24-bit data .................................................................................... .............. 32 figure 14.i2s up to 24-bit data ............................................................................................... .................. 32 figure 15.right-justified 16-bit data, right-justified 24-bit data ............................................................ 32 figure 16.analog input architecture ........................................................................................... ............... 33 figure 17.de-emphasis curve ................................................................................................... ............... 35 figure 18.analog output architecture ............. ............................................................................. ............. 36 figure 19.initialization flow ch art ........................................................................................... .................. 39 figure 20.software mode timing, i2c write ..................................................................................... ......... 41 figure 21.software mode timing, i2c read ...................................................................................... ........ 41 figure 22.software mode timing, spi mode ...................................................................................... ...... 43 figure 23.single-sp eed mode stopband rejection ................................................................................ .. 65 figure 24.single-sp eed mode transition band . .................................................................................. ..... 65 figure 25.single-speed mode transition band (det ail) .......................................................................... .. 65 figure 26.single-sp eed mode passband ripple ................................................................................... ... 65 figure 27.double-speed mode stopb and rejection ................................................................................ .65 figure 28.double-speed mo de transition band ................................................................................... .... 65 figure 29.double-speed mode transition band (detail) .......................................................................... 66 figure 30.double-speed mode passba nd ripple ................................................................................... .. 66 figure 31.single-sp eed stopband rejection ..................................................................................... ....... 67 figure 32.single-sp eed transition band ..... ................................................................................... .......... 67 figure 33.single-speed transition band (detail) ............................................................................... ....... 67 figure 34.single-speed passband ripple ........................................................................................ ........ 67 figure 35.double-speed stopband rejection ..................................................................................... ...... 67 figure 36.double-speed transition band .............. .......................................................................... ......... 67 figure 37.double-speed transition ba nd (detail) ............................................................................... ...... 68 figure 38.double-speed passband ripple ........................................................................................ ....... 68 figure 39.quad-speed stopband rejection ....................................................................................... ...... 68 figure 40.quad-speed transition band .......................................................................................... ......... 68 figure 41.quad-speed transition band (detail) ................................................................................. ...... 68 figure 42.quad-speed passband ripple .......................................................................................... ....... 68 list of tables table 1. i/o power rails ...................................................................................................... ..................... 12 table 2. speed modes .......................................................................................................... .................... 28 table 3. single-speed mode common clock frequencies ...................................................................... 28 table 4. double-speed mode common clock frequencies ..................................................................... 28 table 5. m1 and m0 mode pins in hardware mode .. ............................................................................... .29 table 6. slave mode sclk/lrck ratios .......................................................................................... ....... 30 table 7. mclkx to lrckx ratios ...................... .......................................................................... ............. 30 table 8. hardware mode interface format control ............................................................................... .... 32
ds721a6 7 cs42324 table 9. hardware mode feature summary ........................................................................................ ..... 40 table 10. freeze-able bits ........................... ......................................................................... .................... 48
8 ds721a6 cs42324 1. pin descriptions 1.1 software mode pin name # pin description sda/cdout 1 i2c format sda ( input/output ) - acts as an input/output data pin. an external pull-up resistor is required for i2c control port operation. spi format cdout ( output ) - acts as an output only data pin. scl/cclk 2 i2c format, scl ( input ) ? serial clock for the serial control port. an external pull-up resistor is required for i2c control port operation. spi format, cclk ( input ) ? serial clock for the serial control port. ad0/cs 3 i2c format, ad0 ( input ) - forms the device address input ad[0]. spi format, cs ( input ) - acts as the active low chip select input. ad1/cdin 4 i2c format, ad1 ( input ) - forms the device address input ad[1]. spi format, cdin ( input ) - becomes the input data pin. int 5 interrupt ( output ) - indicates an interrupt condition has occurred. filt+ 6 filt+ ( output ) - full-scale reference voltage for adc. vcmadc 7 adc common-mode voltage ( output ) - filter connections for the adc internal quiescent refer- ence voltage. gnd 8 analog ground ( input ) - analog ground reference. va 9 analog power (input) - positive power for the internal analog section. vbias 10 bias voltage ( output ) - positive reference voltage for the internal dac. mutec1 11 mute control 1 ( output ) - active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. this pin will become a high-impedance out- put during power-down mode or when an invalid mclk to lrck ratio is detected. ovfl scl/cclk gndh sclk1 ad0/cs ad1/cdin int sda/cdout filt+ vcmadc gnd va vbias mutec1 mutec2 va_h aout1b aout2a aout2b aout3a aout3b mutec3 vcmbuf vcmdac va_h aout1a rst ain1a ain1b ain2a ain2b ain3a ain3b ain4a ain4b ain5a ain5b sdin2 mclk1 lrck1 vd gnd vl sdout sclk2 lrck2 mclk2 sdin1 6 2 4 8 1 3 5 7 9 11 12 31 35 33 29 27 36 34 32 30 28 26 25 10 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 cs42324
ds721a6 9 cs42324 mutec2 12 mute control 2 ( output ) - active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail out put. this pin will becom e a high-impedance out- put during power-down mode or when an invalid mclk to lrck ratio is detected. mutec3 13 mute control 3 ( output ) - active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail out put. this pin will becom e a high-impedance out- put during power-down mode or when an invalid mclk to lrck ratio is detected. vcmbuf 14 vcmbuf ( output ) - internally buffered vcmdac vcmdac 15 dac common-mode voltage ( output ) - filter connections for the dac internal quiescent refer- ence voltage. va_h 16 18 analog high voltage power (input) - positive power for the internal output buffer section. gndh 17 analog ground ( input ) - ground reference for high-voltage section. aout1a, aout1b aout2a, aout2b aout3a, aout3b 19, 20 21, 22 23, 24 dac analog audio outputs ( output ) - the full-scale output level is specified in the dac analog characteristics specification table. ain5b, ain5a ain4b, ain4a ain3b, ain3a ain2b, ain2a ain1b, ain1a 25, 26 27, 28 29, 30 31, 32 33, 34 stereo analog inputs 1-5 ( input ) - the full-scale input level is specified in the adc analog char- acteristics specification table. rst 35 reset ( input ) - the device enters a low-power mode when this pin is driven low. ovfl 36 adc overflow ( output ) - indicates an adc overflow condition is present. sdin2 sdin1 37 38 serial audio data input ( input ) - input for two?s complement serial audio data. mclk2 39 master clock 2 ( input ) - optional asynchronous clock source for the dac?s delta-sigma modula- tors. lrck2 40 serial port 2 left/right clock (input/output ) - determines which channel, left or right, is cur- rently active on the serial audio input data line. sclk2 41 serial port 2 serial bit clock (input/output ) - serial bit clock for serial audio interface 2. vd 42 digital power ( input ) - positive power for the internal digital section. gnd 43 digital ground ( input ) - ground reference for the internal digital section. vl 44 digital interface power ( input ) - determines the required signal level for the control and serial port interfaces as shown in ?i/o power rails? on page 12 . refer to the ?recommended operating conditions? on page 13 for appropriate voltages. sdout 45 serial audio data output ( output ) - output for two?s complement serial audio data. sclk1 46 serial port 1 serial bit clock (input/output ) - serial bit clock for serial audio interface 1. lrck1 47 serial port 1 left/right clock (input/output ) - determines which channel, left or right, is cur- rently active on the serial audio output data line. mclk1 48 master clock 1 ( input ) - clock source for the adc?s delta-sigma modulators. by default, this sig- nal also clocks the dac?s delta-sigma modulators.
10 ds721a6 cs42324 1.2 hardware mode pin name # pin description m0, m1 1, 2 mode selection ( input ) - determines the operational mode of the device. mdiv 3 mclk divider ( input ) - setting this pin high places a divide-by-2 circuit in the mclk path to the core device circuitry. mute 4 mute ( input ) - engages the internal digital mute and activates the mutecx pins dif 5 dif ( input ) - sets the serial audio interface format. setting dif high selects i2s audio format and low selects lj audio format. filt+ 6 filt+ ( output ) - full-scale reference voltage for adc. vcmadc 7 adc common-mode voltage ( output ) - filter connections for the adc internal quiescent refer- ence voltage. gnd 8 analog ground ( input ) - analog ground reference. va 9 analog power (input) - positive power for the internal analog section. vbias 10 bias voltage ( output ) - positive reference voltage for the internal dac. mutec1 11 mute control 1 ( output ) - active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. this pin will become a high-impedance out- put during power-down mode or when an invalid mclk to lrck ratio is detected. mutec2 12 mute control 2 ( output ) - active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. this pin will become a high-impedance out- put during power-down mode or when an invalid mclk to lrck ratio is detected. 6 2 4 8 1 3 5 7 9 11 12 31 35 33 29 27 36 34 32 30 28 26 25 10 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 ovfl rst ain1a ain1b ain2a ain2b ain3a ain3b ain4a ain4b ain5a ain5b m1 mdiv mute dif m0 filt+ vcmadc gnd va vbias mutec1 mutec2 sclk1 sdin2 mclk1 lrck1 vd gnd vl sdout sclk2 lrck2 mclk2 sdin1 gndh va_h aout1b aout2a aout2b aout3a aout3b mutec3 vcmbuf vcmdac va_h aout1a cs42324
ds721a6 11 cs42324 mutec3 13 mute control 3 ( output ) - active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail out put. this pin will becom e a high-impedance out- put during power-down mode or when an invalid mclk to lrck ratio is detected. vcmbuf 14 vcmbuf ( output ) - internally buffered vcmdac vcmdac 15 dac common-mode voltage ( output ) - filter connections for the dac internal quiescent refer- ence voltage. va_h 16, 18 analog high voltage power (input) - positive power for the internal output buffer section. gndh 17 analog ground ( input ) - ground reference for high-voltage section. aout1a, aout1b aout2a, aout2b aout3a, aout3b 19, 20 21, 22 23, 24 dac analog audio outputs ( output ) - the full-scale output level is specified in the dac analog characteristics specification table. ain5b, ain5a ain4b, ain4a ain3b, ain3a ain2b, ain2a ain1b, ain1a 25, 26 27, 28 29, 30 31, 32 33, 34 stereo analog inputs 1-5 ( input ) - the full-scale input level is specified in the adc analog char- acteristics specification table. rst 35 reset ( input ) - the device enters a low-power mode when this pin is driven low. ovfl 36 adc overflow ( output ) - indicates an adc overflow condition is present. sdin2 sdin1 37 38 serial audio data input ( input ) - input for two?s complement serial audio data. mclk2 39 master clock 2 ( input ) - optional asynchronous clock source for the dac?s delta-sigma modula- tors. lrck2 40 serial port 2 left/right clock (input/output ) - determines which channel, left or right, is cur- rently active on the serial audio input data line. sclk2 41 serial port 2 serial bit clock (input/output ) - serial bit clock for serial audio interface 2. vd 42 digital power ( input ) - positive power for the internal digital section. gnd 43 digital ground ( input ) - ground reference for the internal digital section. vl 44 digital interface power ( input ) - determines the required signal level for the control and serial port interfaces as shown in ?i/o power rails? on page 12 . refer to the ?recommended operating conditions? on page 13 for appropriate voltages sdout 45 serial audio data output ( output ) - output for two?s complement serial audio data. sclk1 46 serial port 1 serial bit clock (input/output ) - serial bit clock for serial audio interface 1. lrck1 47 serial port 1 left right/clock (input/output ) - determines which channel, left or right, is cur- rently active on the serial audio output data line. mclk1 48 master clock 1 ( input ) - clock source for the adc?s delta-sigma modulators. by default, this sig- nal also clocks the dac?s delta-sigma modulators.
12 ds721a6 cs42324 1.3 digital i/o pin characteristics the logic level for each input should adhere to the corresponding power rail and should not exceed the max- imum ratings. power supply pin number pin name i/o driver receiver software mode vl 1sda cdout input/output hi-z/output 1.8 v - 3.3 v, open drain 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v, with hysteresis 2 scl cclk input - 1.8 v - 3.3 v, with hysteresis 3 ad0 cs input - 1.8 v - 3.3 v, with hysteresis 4 ad1 cdin input - 1.8 v - 3.3 v, with hysteresis 5 int output 1.8 v - 3.3 v, open dr ain 1.8 v - 3.3 v, with hysteresis hardware mode vl 1 m0 input - 1.8 v - 3.3 v, with hysteresis 2 m1 input - 1.8 v - 3.3 v, with hysteresis 3 mdiv input - 1.8 v - 3.3 v, with hysteresis 4 mute input - 1.8 v - 3.3 v, with hysteresis 5 dif input - 1.8 v - 3.3 v, with hysteresis all modes vl 35 rst input - 1.8 v - 3.3 v 47 40 lrck1 lrck2 input/output 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v 46 41 sclk1 sclk2 input/output 1.8 v - 3.3 v, cmos 1.8 v - 3.3 v 48 39 mclk1 mclk2 input - 1.8 v - 3.3 v 38 37 sdin1 sdin2 input - 1.8 v - 3.3 v 45 sdout output 1.8 v - 3.3 v, cmos - 36 ovfl output 1.8 v - 3.3 v, open drain - va_h 11 12 13 mutec1 mutec2 mutec3 output 9.0 v - 12.0 v - table 1. i/o power rails
ds721a6 13 cs42324 2. characteristics and specifications recommended operating conditions gnd = gndh = 0 v; all voltages with respect to ground. absolute maximum ratings gnd = gndh = 0 v; all voltages with respect to ground. (note 1) notes: 1. operation beyond these limits may result in permanent damage to the device. normal operation is not guar anteed at these extremes. 2. any pin except supplies. transien t currents of up to 100 ma on the analog input pins will not cause scr latch-up. parameters symbol min nom max units dc power supplies: analog digital logic high voltage analog va vd vl va_h 3.13 3.13 1.71 8.55 3.3 3.3 3.3 9.0 3.47 3.47 3.47 12.60 v v v v ambient operating temper ature (power applied) commercial(-cqz) automotive(-dqz) t a -40 -40 - - +85 +105 c c parameter symbol min max units dc power supplies: analog digital logic high voltage analog va vd vl va_h -0.3 -0.3 -0.3 -0.3 +4.50 +4.50 +4.50 +17.0 v v v v input current (note 2) i in -10 + 10 ma analog input voltage v ina gnd - 0.3 va_h + 0.3 v digital input voltage logic v ind -0.3 vl + 0.4 v ambient operating temper ature (power applied) t a -55 +125 c storage temperature t stg -65 +150 c
14 ds721a6 cs42324 dac analog characteristic s - commercial (-cqz) test conditions (unless otherwis e specified): va = vd = vl = 3.3 v, va_h = 9 v, gnd = gndh = 0 v; t a = 25 c; 997 hz full-scale output sine wave. decoupling capacitors, filter capacitors, and recommended output filter as shown in figure 7 on page 26 and figure 8 on page 27 ; fs = 48 khz or 96 khz; synchronous mode; measurement bandwidth 10 hz to 20 khz, notes: 3. one-half lsb of triangular pdf dither added to data. 4. see figures 1 and 2 on page 16 . r l and c l reflect the minimum resistan ce and maximum capacitance allowed in order to maintain st ability in the internal op-amp. c l affects the dominant pole of the internal output amp; increasing c l beyond 100 pf can cause the internal op-amp to become unstable. parameter symbol min typ max unit dynamic range (note 3) 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 94 91 88 85 100 97 93 90 - - - - db db db db total harmonic distortion + noise (note 3) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -90 -77 -37 -87 -77 -37 -84 -73 -33 -82 -62 -22 db db db db db db interchannel isolation (1 khz) - -100 - db dc accuracy interchannel gain mismatch - 0.1 0.25 db gain drift - 100 - ppm/c analog output full-scale output voltage 1.9 2.0 2.1 v rms max current draw from an aout pin i out - 575 - a ac-load resistance (note 4) r l 5--k load capacitance (note 4) c l --100pf output impedance z out -50-
ds721a6 15 cs42324 dac analog characteristi cs - automotive (-dqz) test conditions (unle ss otherwise specified): va = 3.13 v to 3.47 v, vd = 3.13 v to 3.47 v, vl = 1.71 v to 3.47 v, va_h = 8.55 v to 12.60 v, gnd = gndh = 0 v; t a = -40 c to +85 c; 997 hz full-scale output sine wave. decoupling capacitors, filter capacitors, a nd recommended output filter as shown in figure 7 on page 26 and fig- ure 8 on page 27 ; fs = 48 khz or 96 khz; synchronous mode; measurement bandwidth 10 hz to 20 khz, parameter symbol min typ max unit dynamic range (note 3) 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 90 87 83 80 100 97 93 90 - - - - db db db db total harmonic distortion + noise (note 3) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -90 -77 -37 -87 -77 -37 -80 -67 -27 -77 -67 -27 db db db db db db interchannel isolation (1 khz) - -100 - db dc accuracy interchannel gain mismatch - 0.1 0.25 db gain drift - 100 - ppm/c analog output full-scale output voltage 1.9 2.0 2.1 v rms max current draw from an aout pin i out -575- a ac-load resistance (note 4) r l 5--k load capacitance (note 4) c l - - 100 pf output impedance z out -50-
16 ds721a6 cs42324 dac combined interpolation & on-chip analog filter response notes: 5. response is clock-dependent and will scale with fs. no te that the amp litude vs. frequency plots of this data ( figures 31 to 42 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 6. for single-speed mode, the measurement bandwidth is from stopband to 3 fs. for double-speed mode, the measurement bandwidth is from stopband to 3 fs. 7. de-emphasis is available only in single-speed mode. parameter (note 5) symbol min typ max unit single-speed mode passband (note 6) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response (10 hz to 20 khz) -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 6) 102 - - db group delay tgd - 9.4/fs - s de-emphasis error (note 7) fs = 44.1 khz - - +/-0.14 db double-speed mode passband (note 6) to -0.01 db corner to -3 db corner 0 0 - - .43 .499 fs fs frequency response (10 hz to 20 khz) -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 6) 80 - - db group delay tgd - 4.6/fs - s aoutx gnd 3.3 f v out r l c l figure 1. equivalent analog output load figure 2. maximum analog output loading 100 50 75 25 2.5 5 10 15 safe operating region capacitive load -- c (pf) l resistive load -- r (k ) l 125 20 10
ds721a6 17 cs42324 adc analog characteristi cs - commercial (-cqz) test conditions (unless otherwise specified): va = vd = vl = 3.3 v, va_h = 9 v, gnd = gndh = 0 v; t a = 25 c; 997 hz input sine wave. decoupling capacitors, filter ca pacitors, and recommended input filter as shown in figure 7 on page 26 and figure 8 on page 27 ; fs = 48 khz or 96 khz; synchronous mode; measurement bandwidth 10 hz to 20 khz, note: 8. referred to the typical line- level full-scale input voltage. parameter symbol min typ max unit single-speed mode dynamic range a-weighted unweighted 89 86 95 92 - - db db total harmonic distortion + noise (note 8) -1 db -20 db -60 db thd+n - - - -88 -72 -32 -80 - - db db db double-speed mode dynamic range a-weighted unweighted 89 86 95 92 - - db db total harmonic distortion + noise (note 8) -1 db -20 db -60 db thd+n - - - -88 -72 -32 -80 - - db db db dc accuracy interchannel gain mismatch - 0.1 - db gain error -5 - + 5% gain drift - 100 - ppm/c analog input characteristics full-scale input voltage 0.576?va 0.606?va 0.636?va v rms input impedance - 200 - k maximum interchannel input impedance mismatch - 2 - % interchannel isolation (1 khz) - -90 - db
18 ds721a6 cs42324 adc analog characteristic s - automotive (-dqz) test conditions (unless otherwise specified): va = 3.13 v to 3.47 v, vd = 3.13 v to 3.47 v, vl = 1.71 v to 3.47 v, va_h = 8.55 v to 12.60 v, gnd = gndh = 0 v; t a = -40 c to +85 c; 997 h z input sine wave. decoupling capacitors, filter capacitors, and re commended input filter as shown in figure 7 on page 26 and figure 8 on page 27 ; fs = 48 khz or 96 khz; synchronous mode; measurement bandwidth 10 hz to 20 khz, note: 9. referred to the typical line- level full-scale input voltage. parameter symbol min typ max unit single-speed mode dynamic range a-weighted unweighted 85 82 95 92 - - db db total harmonic distortion + noise (note 8) -1 db -20 db -60 db thd+n - - - -88 -72 -32 -78 - - db db db double-speed mode dynamic range a-weighted unweighted 85 82 95 92 - - db db total harmonic distortion + noise (note 8) -1 db -20 db -60 db thd+n - - - -88 -72 -32 -78 - - db db db dc accuracy interchannel gain mismatch - 0.1 - db gain error -5 - + 5% gain drift - 100 - ppm/c analog input characteristics full-scale input voltage 0.576?va 0.606?va 0.636?va v rms input impedance - 200 - k maximum interchannel input impedance mismatch - 2 - % interchannel isolation (1 khz) - -90 - db
ds721a6 19 cs42324 adc digital filter characteristics notes: 10. response is clock dependent and will scale with sa mple rate (fs). note th at the response plots ( figures 23 to 30 ) are normalized to fs and can be de-normaliz ed by multiplying the x-axis scale by fs. 11. response shown is for fs = 48 khz. parameter (note 10) symbol min typ max unit single-speed mode passband (-0.1 db) 0 - 0.489 fs passband ripple - - 0.035 db stopband 0.569 - - fs stopband attenuation 70 - - db total group delay t gd -12/fs - s double-speed mode passband (-0.1 db) 0 - 0.489 fs passband ripple - - 0.025 db stopband 0.5604 - - fs stopband attenuation 69 - - db total group delay t gd -9/fs - s high-pass filter characteristics frequency response -3.0 db -0.13 db (note 11) -1 20 - - hz hz phase deviation @ 20 hz (note 11) -10 -deg passband ripple -- 0db filter settling time 10 5 /fs s
20 ds721a6 cs42324 analog pass-thru characteristics test conditions (unless otherwise specified): va = vd = vl = 3.3 v; va_h = 9 v; gnd = gndh = 0 v; t a = 25 c; input test signal is a 1 khz sine wave; measurem ent bandwidth is 10 hz to 20 khz; synchronous mode. note: 12. referred to the typical line- level full-scale input voltage. parameter symbol min typ max unit analog input to analog output characteristics (gain=0db) dynamic range a-weighted unweighted 89 86 95 92 - - db db total harmonic distortion + noise (note 8) 0db -3 db thd+n - - -87 -93 -81 - db db frequency response 10 hz to 20 khz - 0.1 - db analog characteristics max input voltage - 2.0 - v rms max output voltage - 2.0 - v rms max current draw from an aout pin i out - 575 - a ac-load resistance (note 4) r l 5- -k load capacitance (note 4) c l - - 100 pf output impedance z out -50- interchannel isolation (1 khz) - -90 - db
ds721a6 21 cs42324 dc electrical characteristics gnd = gndh = 0 v; all voltages with respect to ground. mclk1=12.288 mhz; mclk2= static; fs=48 khz; master mode. notes: 13. power-down mode is defined as rst = low, with all clock and data lines held static low and no analog input. 14. valid with the recommended capacitor values on filt+, vcmdac, vcmadc and vcmbuf as shown in figure 7 on page 26 and figure 8 on page 27 . 15. the dc current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors. digital interface characteristics note: 16. digital interface signals include all pins sourced from the vl supply as shown in ?i/o power rails? on page 12 . parameter symbol min typ max unit power supply current (no rmal operation) va_h = 9 v va = 3.3 v vd = 3.3 v vl = 3.3 v i a_h i a i d i l - - - - 24 19 22 10 32 25 29 13 ma ma ma ma power supply current va _h= 9 v (power-down mode) (note 13) vl=vd=va=3.3 v i pd - - 0 200 - - a a power consumption (normal operation) va_h = 9 v vl=vd=va = 3.3 v (power-down mode) all supplies - - - - - - 216 169 0.7 289 225 - mw mw mw power supply rejection ratio (1 khz) (note 14) psrr - 60 - db reference voltages vcmadc nominal voltage vcmadc - 0.5?va - v vcmdac nominal voltage vcmdac - 4 - v dc current from vcmadc or vcmdac (note 15) i cm -- 1 a vcmadc or vcmdac output impedance z cm -23 -k filt+ nominal voltage filt+ - va - v vbias nominal voltage vbias - va-0.8 - v parameters (note 16) symbol min typ max units high-level input voltage v ih 0.7?vl - - v low-level input voltage v il - - 0.2?vl v high-level output voltage at i o =2 ma digital interface mutec1 /mutec2 /mutec3 v oh v oh vl-1.0 va_h-1.0 - - - - v v low-level output voltage at i o =2 ma digital interface mutec1 /mutec2 /mutec3 v ol v ol - - - - 0.4 0.4 v v input leakage current i in -10 - +10 a input capacitance - - 1 pf maximum mutec1 /mutec2 /mutec3 drive current -3-ma minimum ovfl active time s 10 6 lrc kx ---------------------
22 ds721a6 cs42324 switching characteristics - serial audio logic ?0? = gnd = gndh = 0 v; logic ?1? = vl; c l = 20 pf. notes: 17. duty cycle of generated sclkx in master mode de pends on duty cycle of the corresponding mclkx as specified under ?system clocking? on page 28 . 18. in slave mode, the sclk/lrck ratio can be set a ccording to preference. however, specified perfor- mance is guaranteed only when using the ratios in section 4.2.1 master mode on page 30 and section 4.2.2 slave mode on page 30 . parameter symbol min typ max unit master clock (mclkx = mclk1, mclk2) mclkx frequency mclkx duty cycle 1.024 40 - 50 41.4720 60 mhz % sample rates single-speed mode double-speed mode - 4 50 - 54 108 khz master mode sclkx frequency sclkx period 1/(128*108 khz) sclkx duty cycle (note 17) - t period t high t period 64?fs 72.3 40 - - 50 64?fs - 60 hz ns % lrckx setup before sclk rising lrckx hold after sclk rising t setup1 t hold1 20 20 --ns sdout setup before sclk rising sdout hold after sclk rising t setup2 t hold2 10 10 --ns slave mode sclkx frequency (note 18) sclkx period 1/(128?108 khz) sclkx duty cycle - t period t high t period - 72.3 40 64?fs - 50 - - 60 hz ns % lrckx setup before sclk rising lrckx hold after sclk rising t setup1 t hold1 20 20 --ns sdout setup before sclk rising sdout hold after sclk rising t setup2 t hold2 10 10 --ns figure 3. serial input timing lrckx sdout sclkx data channel channel data t hold2 t setup2 t hold1 t setup1 t period t high
ds721a6 23 cs42324 switching characteristics - serial audio (cont.) logic ?0? = gnd = gndh = 0 v; logic ?1? = vl; c l = 20 pf. parameter symbol min typ max unit master mode sdinx setup before sclk rising sdinx hold after sclk rising t setup3 t hold3 10 10 --ns slave mode sdinx setup before sclk rising sdinx hold after sclk rising t setup3 t hold3 10 10 --ns figure 4. serial output timing lrckx sdinx sclkx data channel channel data t hold3 t setup3 t hold1 t setup1 t period t high
24 ds721a6 cs42324 switching characteristics - software mode - i2c format inputs: logic ?0? = gnd = gndh = 0 v, logic ?1? = vl, c l =30pf) note: 19. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note note:) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 5. software mode timing - i2c format
ds721a6 25 cs42324 switching characteristics - so ftware mode - spi format inputs: logic ?0? = gnd = gndh = 0 v; logic ?1? = vlc; c l =20pf. notes: 20. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 21. data must be held for sufficient time to bridge the transition time of cclk. 22. for f sck < 1 mhz. 23. cdout should not be sampled during this time. figure 6. software mode timing - spi mode parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 20) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 21) t dh 15 - ns rise time of cclk and cdin (note 22) t r2 -100ns fall time of cclk and cdin (note 22) t f2 -100ns transition time from cclk to cdout valid (note 23) t r2 -100ns time from cs rising to cdout high-z t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst cdout t scdov t scdov t cscdo hi-impedance
26 ds721a6 cs42324 3. typical connection diagrams figure 7. typical connection diagram - software mode mutec1 vl 0.1 f +1.8v to +3.3v scl/cclk sda/cdout ad0/cs rst 2 k see note 1 lrck2 sdin1 note 1: resistors are required for i2c control port operation soc/dsp mclk2 sclk2 * capacitors must be c0g or equivalent lrck1 sdout mclk1 sclk1 vbias ovfl 1 f 0.1 f vcmadc filt+ 1 f gnd aout1a aout1b 470 470 3.3 f c optional analog muting 2 k 3.3 f int 10 k 10 k c * see note 2 for best response to fs/2 : () 470 4 470 + = ext ext r fs r c this circuitry is intended for applications where the cs42324 connects directly to a line level output. for internal routing applications please see the dac analog output characteristics section for loading limitations . r ext is the load impedance. note 2 : ain1a ain1b ain2a ain2b ain3a ain3b ain4a ain4b ain5a ain5b 0.1 f 3.3 f 0.1 f vcmdac vcmbuf 3.3 f 0.1 f * * va 10 f +3.3 v 0.1 f 10 f 0.1 f va_h vd +9 v to +12 v 1 f 2 vrms right analog in 5 mutec2 aout2a aout2b 470 470 3.3 f c optional analog muting 3.3 f 10 k 10 k c * see note 2 * * mutec3 aout3a aout3b 470 470 3.3 f c optional analog muting 3.3 f 10 k 10 k c * see note 2 * * +3.3 v 0.1 f 10 f sdin2 2 vrms left analog out 1 2 vrms right analog out 1 2 vrms left analog out 2 2 vrms right analog out 2 2 vrms left analog out 3 2 vrms right analog out 3 1 f 2 vrms left analog in 2 1 f 2 vrms left analog in 5 1 f 2 vrms right analog in 4 1 f 2 vrms left analog in 4 1 f 2 vrms right analog in 3 1 f 2 vrms left analog in 3 1 f 2 vrms right analog in 2 1 f 2 vrms right analog in 1 1 f 2 vrms left analog in 1 3.3 f cs42324 va_h gnd gndh ad1/cdin
ds721a6 27 cs42324 mutec1 * capacitors must be c0g or equivalent vbias 1 f 0.1 f vcmadc filt+ 1 f gnd aout1a aout1b 470 470 3.3 f c optional analog muting 3.3 f 10 k 10 k c * see note 1 for best response to fs/2 : () 470 4 470 + = ext ext r fs r c this circuitry is intended for applications where the cs42324 connects directly to a line level output. for internal routing applications please see the dac analog output characteristics section for loading limitations. r ext is the load impedance. note 1 : ain1a ain1b ain2a ain2b ain3a ain3b ain4a ain4b ain5a ain5b 0.1 f 3.3 f 0.1 f vcmdac vcmbuf 3.3 f 0.1 f * * va +3.3 v 1 f 2 vrms right analog in 5 mutec2 aout2a aout2b 470 470 3.3 f c optional analog muting 3.3 f 10 k 10 k c * see note 1 * * mutec3 aout3a aout3b 470 470 3.3 f c optional analog muting 3.3 f 10 k 10 k c * see note 1 * * 0.1 f 10 f 2 vrms left analog out 1 2 vrms right analog out 1 2 vrms left analog out 2 2 vrms right analog out 2 2 vrms left analog out 3 2 vrms right analog out 3 1 f 2 vrms left analog in 2 1 f 2 vrms left analog in 5 1 f 2 vrms right analog in 4 1 f 2 vrms left analog in 4 1 f 2 vrms right analog in 3 1 f 2 vrms left analog in 3 1 f 2 vrms right analog in 2 1 f 2 vrms right analog in 1 1 f 2 vrms left analog in 1 3.3 f cs42324 vl 0.1 f +1.8v to +3.3v soc/dsp m0 rst lrck2 sdin1 mclk2 sclk2 lrck1 sdout mclk1 sclk1 sdin2 m1 dif ovfl mdiv mute 5 k vl * see note 2 pull-up on sdout indicates hardware mode operation note 2 : 10 f 0.1 f 10 f 0.1 f va_h vd +9 v to +12 v +3.3 v va_h gnd gndh figure 8. typical connection diagram - hardware mode
28 ds721a6 cs42324 4. applications 4.1 system clocking the cs42324 will oper ate at sampling fr equencies from 4 khz to 108 khz. this range is divided into two speed modes as shown in table 2 . the cs42324 has two serial ports which can operate synchronously or asynchronously. serial port 1 (sp1) consists of the sclk1 and lrck1 signals. seri al port 2 (sp2) consists of the sclk2 and lrck2 signals. the serial audio output, sdout, and serial audio inputs, sdin1 and sdin2, can be independent- ly assigned to either of the two serial ports for ease of clocking. each serial port may be independently placed into single- or double-speed mode. the serial ports may also be independently placed into master or slave mode. 4.1.1 master clock in both synchronous and asynchronous modes, mclk x (mclk1 and/or mclk2) and the corresponding lrckx must maintain an integer ratio. some common ratios are shown in tables 3 and 4 . the lrckx frequency is equal to fs, the frequency at which audi o samples for each channel are clocked into or out of the device. the sp1_speed and sp2_speed bits and the mclkx freq bits configure the device to generate the proper clocks in master mode and rece ive the proper clocks in slave mode when auto detect mode is disabled. tables 3 and 4 illustrate several standard audio sa mple rates and th e required mclkx and lrckx frequencies. speed mode master mode sampling frequency slave mode sampling frequency single-speed 4-54 khz 4-54 khz double-speed 50-108 khz 50-108 khz table 2. speed modes mode lrckx (khz) mclkx (mhz) 128x 192x 256x 384x 512x 768x single speed mode (ssm) 32 - - 8.1920 12.2880 16.3840 24.5760 44.1 - - 11.2896 16.9344 22.5792 33.8680 48 - - 12.2880 18.4320 24.5760 36.8640 mclkx freq [1:0] - - 00011011 mdiv pin - - 0 - 1 - table 3. single-speed mode common clock frequencies mode lrckx (khz) mclkx (mhz) 128x 192x 256x 384x 512x 768x double speed mode (dsm) 64 8.1920 12.2880 16.3840 24.5760 - - 88.2 11.2896 16.9344 22.5792 33.8680 - - 96 12.2880 18.4320 24.5760 36.8640 - - mclkx freq [1:0] 00011011 - - mdiv pin 0 - 1 - - - table 4. double-speed mode common clock frequencies
ds721a6 29 cs42324 4.1.2 synchronous / asynchronous mode by default, the cs42324 operates in synchronous mo de with both serial ports synchronous to mclk1. in this mode, the serial po rts may operate at differ ent synchronous rates as set by the sp1_speed and sp2_speed bits, and mclk2 does not need to be provided (the mclk 2 pin should be left unconnected if not required). if the spx_mclk (spx = sp1 and/or sp2) bits in serial ports 1 and 2 are set differently, the cs42324 will operate in asynchronous mode. the serial ports will operate asynchronously with serial port 1 clocked from its sp1_mclk selection and serial port 2 clocke d from its sp2_mclk selection. in this mode, the serial ports may operate at different asynchronous rates. in hardware mode mclk1 is the master clock source for all internal circuits. clock selection and asyn- chronous operation are not available. 4.2 serial port operation each cs42324 serial audio interface port operates as either a clock slave or master. they accept externally generated clocks in slave mode (lrckx and sclk x pins are inputs, generated clocks shown in figure 9 are disabled) and will generate synch ronous clocks derived from an in put master clock (mclk1/mclk2) in master mode (lrckx and sclkx pins are outputs, generated clocks shown in figure 9 are enabled). the lrck, fs, is the frequency at which audio samples for each channel are clocked into or out of the de- vice. in slave mode, lrck should be synchronously derived from the mclk selected in spx_mclk regis- ter. the sclk is the bit clock which is used to clock in th e serial audio data stream. sclk should adhere to the timing requirements outlined in ?switching characteristics - serial audio? on page 22 . the sp1_speed, sp2_speed, mclk1 freq [1:0] and mclk2 freq[1:0] soft ware mode control bits or the m1, m0, and mdiv hardware control pins, configure the device to generate the proper clocks in master mode and receive the proper clocks in slave mode. in hardware mode, control pins m1 and m0 configure the master/slave mode setting for the serial ports as well as the speed mode as shown in table 5 . m0 (pin 1) m1 (pin 2) serial port configuration 0 0 clock master, single-speed mode 0 1 clock master, double-speed mode 10reserved 1 1 clock slave, auto-detect speed mode table 5. m1 and m0 mode pins in hardware mode serial port 1 (sp1) lrck1 pin generated-lrck1 internal-lrck1 to converters sp1_m/s sclk1 pin generated-sclk1 internal-sclk1 to converters sp1_m/s master mode clock generation serial port 2 (sp2) lrck2 pin generated-lrck2 internal-lrck2 to converters sp2_m/s sclk2 pin generated-sclk2 internal-sclk2 to converters sp2_m/s master mode clock generation figure 9. serial port topology figure 10 on page 30 figure 10 on page 30
30 ds721a6 cs42324 4.2.1 master mode as a clock master, the lrckx and sclk x of each serial port will operate as outputs. the two serial ports may be independently placed into master or slave mode. each lrckx and sclkx are internally derived from the mclkx selected by the sp1_mclk and sp2_mclk signals as shown in figure 10 . 4.2.2 slave mode in slave mode, sclkx and lrckx operate as inputs. each serial port may be independently placed into slave mode. the left/right clock signal, lrckx, must be equal to the sample rate, fs. the serial bit clock, sclkx, must be equal to 128x, 64x, 48x, or 32x fs depending on the desired speed mode. refer to table 6 for required serial bit cloc k to left/right clock ratios. if operating in asynchronous mode, lrck1 and sclk1 must be synchronously derived from the sp1?s selected mclk, and lrck2 and sclk2 must be synchronously derived from sp2?s selected mclk. if operating in synchronous mode, sclk1, lrck1, sclk2 and lrck2 must be synchronously derived from the same mclk. for more information on synchronous and asynchronous modes, see ?synchro- nous / asynchronous mode? on page 29 . the speed of each serial port is automatically determined based on the input mclkx to lrckx ratio when the auto-detect functi on is enabled. certain input clock ratios will then require an in ternal divide-by-two of mclkx using either the mclkx freq bits or the mdiv hardware control pin. serial data format sclkx to lrckx ratio single speed mode double speed mode i2s, lj or rj data format 32, 48, 64, 128 32, 48, 64 table 6. slave mode sclk/lrck ratios mode mclkx to lrckx ratio single speed mode double speed mode sw auto mode detect 256, 384, 512, 768 128, 192, 256, 384 hw auto mode detect 256, 512 128, 256 see table 3 an table 4 on page 28 for clock ratio configuration. table 7. mclkx to lrckx ratios 256 128 4 2 0 1 generated-lrck1 generated-sclk1 00 01 10 1 1.5 2 11 3 mclk1 256 128 4 2 generated-lrck2 generated-sclk2 0 1 sp2_speed sp1_speed sp2_mclk mclk1 freq[1:0] 0 1 0 1 0 1 00 01 10 1 1.5 2 11 3 mclk2 mclk2 freq[1:0] 0 1 sp1_mclk internal-mclk1 internal-mclk2 figure 10. master mode clock generation
ds721a6 31 cs42324 4.2.3 adc, dac1, and dac2 clock selection the adc, dac1, and dac2 can be independently set to use either of the two serial ports as a clock source. each also has control over wh ich mclk to use. this allows for fu ll flexibility in configuration of the converter. master/slave control is achieved at the serial port level (see figure 9 on page 29 ); the internal converters discussed here are always slave. each converter has a bit in the re gisters (xxx_sp, where xxx = adc, dac1, or dac2) which allows se- lection of the sclk/lrck pair used for the converter. the xxx_mclk bits select which mclk source to use for the converter. if the serial port selected for use is in master mode, this selection must be the same as the mclk_spx for the serial port which is in us e. in slave mode the mclk selected must be synchro- nous to the lrck/sclk selected by xxx_sp. 4.2.4 high-impedance digital output each serial port may be placed on a clock/data bus that allows multiple masters, without the need for ex- ternal buffers. the 3st_sp1, 3st_sp2 and 3st_sdout bi ts place the internal buffers for the serial port signals in a high-impedance state, allowing another device to transmit clocks or data without bus conten- tion. adc internal-lrck1 internal-sclk1 0 1 adc_mclk internal-mclk1 internal-mclk2 0 1 0 1 adc_sp internal-lrck2 internal-sclk2 sdout adc_dif[2:0] dac1 0 1 dac1_mclk internal-mclk1 internal-mclk2 0 1 0 1 dac1_sp sdin1 dac1_dif[2:0] dac2 0 1 dac2_mclk internal-mclk1 internal-mclk2 0 1 0 1 dac2_sp sdin2 dac2_dif[2:0] internal-lrck1 internal-sclk1 internal-lrck2 internal-sclk2 internal-lrck1 internal-sclk1 internal-lrck2 internal-sclk2 figure 11. converter clocking cs42324 transmitting device #1 transmitting device #2 receiving device 3st_spx sdout sclkx/lrckx 3st_sdout figure 12. tri-state serial port
32 ds721a6 cs42324 4.2.5 digital interface formats each converter (adc, dac1, and dac2) has independent selection for serial formats (i2s, left-justified, etc.). data is clocked out of the adc or into the dac on the rising edge of sclk. figures 13 - 17 illustrate the general structure of each format. refer to ?switching characteristics - serial audio? on page 22 or ?switching characteristics - serial audio (cont.)? on page 23 for exact timing relationship between clocks and data. for a complete overview of serial audio interface formats, please reference application note an282. 4.2.6 synchronization of multiple devices in systems where multiple adcs and dacs are required, care mu st be taken to achieve simultaneous sampling. to ensure synchronous sampling, the master clocks and left/right cloc ks must be the same for all of the cs42324?s in the system. if only one master clock source is needed, one solution is to place one cs42324 in master mode, and slave all of the other devices to the one master. dif (pin 5) setting selection lo left-justified interface hi i2s interface table 8. hardware mode interface format control lrckx sclkx msb lsb msb lsb aoutxa left channel right channel sdout sdin1/2 aoutxb msb ainxa ainxb figure 13. left-justified up to 24-bit data lrckx sclkx msb lsb msb lsb aoutxa left channel right channel sdout sdin1/2 aoutxb msb ainxa ainxb figure 14. i2s up to 24-bit data lrckx sclkx msb lsb msb lsb aoutxa left channel right channel sdout sdin1/2 aoutxb ainxa ainxb figure 15. right-justified 16-bit data, right-justified 24-bit data
ds721a6 33 cs42324 4.3 analog-to-digital data path 4.3.1 adc analog input multiplexer ainxa and ainxb are the analog inputs, internally biased to vcmadc. the cs42324 contains a stereo 5-to-1 analog input mu ltiplexer which can select one of 5 possibl e stereo analog input sources and route it to the adc. figure 16 shows the architecture of the input multiplexer. ? section 6.9 ?adc control (address 0ah)? on page 52 ? outlines the bit settings necessary to control the in- put multiplexer. by default, line level input 1 is selected. 4.3.2 adc description the adc analog modulator samples the input at 6.144 mhz (mclk=12. 288 mhz). the digital filter will reject signals within the stopband of the filter. howeve r, there is no rejection for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,... refer to the typical connection dia- gram for the recommended an alog input circuit that will attenuate noise energy at 6.144 mhz. the use of capacitors which have a large voltage coefficient (s uch as general purpose ceramics) must be avoided since these can degrade signal linearity. any unus ed analog input pairs should be left unconnected. the adc output data is in two?s complement binary form at. for inputs above positive full-scale or below negative full-scale, the ad c will output 7fffffh or 8 00000h, respectively and cause the adc overflow bit to be set to a ?1?. given the two?s complement format, low-level signals may cause the msb of the serial data to periodically toggle between ?1? and ?0?, possibly introducing noise into the system as the bi t switches back and forth. to prevent this phenomena, a constant dc offset is ad ded to the serial data bringing the low-level signal just above the point at which the msb would norma lly toggle, thus reducing the noise introduced. note that this offset is not removed (refer to ?adc analog characteristics - commercial (-cqz)? on page 17 for the specified offset level). mux ain1a ain2a ain3a ain5a ain4a ain_sel[2:0] out to adc channel a out to adc channel b mux ain1b ain2b ain3b ain5b ain4b figure 16. analog input architecture
34 ds721a6 cs42324 4.3.3 high-pass filter an d dc offset calibration when using operational amp lifiers in the input circui try driving the cs42324, a small dc offset may be driven into the a/d converter. the cs42324 includes a high-pass filter after the decimator to remove any dc offset which could result in reco rding a dc level, possibly yielding clicks when switching between de- vices in a multichannel system. the high-pass filter continuously subtracts a measure of the dc offset from the output of the decimation filter. if the hpffreeze bit is set during normal opera tion, the current value of the dc offset for the each channel is frozen and this dc offset will continue to be subtracted from the conversion result. this feature makes it possible to perform a system dc offset calibration by: 1. running the cs42324 with the high-pass filt er enabled until the filter settles. see ?adc digital filter characteristics? on page 19 for filter settling time. 2. disabling the high-pass filter and freezing th e stored dc offset for continuous subtraction. a system calibration performed in th is way eliminates offsets anywhere in the signal path between the calibration point and the cs42324. 4.3.4 digital attenuation control digital attenuation control functions are implemented, offering independent channel control for the adc pcm signal path. the volume controls are programmable to ramp in increments of 0.5 db at a rate con- trolled by the adc soft ramp. each adc signal path may also be independently mute d via mute control bits. when enabled, each bit attenuates the signal to its maximum value. when the mute bit is disabled, the signal returns to the atten- uation level set in the respective vo lume control register. the attenuation is ramped up and down at the rate specified by the adc_soft. 4.4 digital-to-analog data path 4.4.1 digital volume control two stereo digital volume control functions are im plemented, offering independent channel control for dac1 and dac2 pcm signal paths into the digital mi xer. the volume controls are programmable to ramp in increments of 0.5 db at a rate controlled by the dac1/2 soft ramp /zero cross settings. each dac1/2 signal path may also be independen tly muted via mute control bits. when enabled, each bit attenuates the signal to its maxi mum value. when the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. the attenuation is ramped up and down at the rate specified by the da c1/2_soft and dac1/2_zc bits. 4.4.2 mono channel mixer independent channel mixers for dac1 and dac2 may be used to create a mix of the left and right chan- nels pcm signals. this mix allows the user to pr oduce a mono signal from a stereo source. the mixer may also be used to implement a left/right channel swap.
ds721a6 35 cs42324 4.4.3 de-emphasis filter the cs42324 includes on-chip digital de-emphasis optimi zed for a sample rate of 44.1 khz. the filter re- sponse is shown in figure 17 . the frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs. the de-emphasis featur e is included to ac commodate audio re cordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. de -emphasis is only available in single-speed mode 4.4.4 internal digital loopback the cs42324 supports an internal digital loopback mode in which the adc?s output data can be internally routed to either of the dac inpu ts. this mode may be activated by setting the dacx_loop_back bit in ?dac1 control (address 0bh)? on page 53 and ?dac2 control (address 0ch)? on page 55 . during this mode, the adc and dac will need to operate at the same synchr onous sample rate. when the dacx_loop_back bit is set, the respective dacx_dif[2 :0] bits must be set to the same value as the adc_dif[2:0] register. during loop back mode, the adc data will continue to be present on the sdout pi n in the format selected by the adc_dif[2:0] bits. 4.4.5 dac description the cs42324 uses a switched current architecture followed by on chip current to voltage conversion and continuous time low-pass f ilter. the digital interpolator response is shown in the ?dac digital filter re- sponse plots? on page 67 . the recommended external analog circuitry is shown in the ?typical connec- tion diagrams? on page 26 . the cs42324 dac does not include phase or amplitude compensation for an external filter. therefore, the dac system phase and amplitude response will be dependent on the exte rnal analog circuitry. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 17. de-emphasis curve
36 ds721a6 cs42324 4.4.6 analog output multiplexer the cs42324 contains three independent stereo 7-to-1 analog output multiplexe rs which can select one of seven possible stereo analog output sources and route it to the ao utxa and aoutxb pins. figure 18 shows the architecture of the analog output multiplexer. ? section 6.12 ?aout1 control (address 0dh)? on page 56 ? and section 6.13 ?aout2 control (address 0eh)? on page 57 outline the bit settings necessary to control the outp ut multiplexer. 4.4.7 output transient control the cs42324 uses popguard technology to minimize the effects of output transients during power-up and power-down. this technique eliminates the audio tr ansients commonly produced by single-ended single- supply converters when it is implemented with extern al dc-blocking capacitors connected in series with the audio outputs. to make best use of this feat ure, it is necessary to understand its operation. 4.4.7.1 power-up when the device is initially powered up, the audi o outputs aoutxa and aoutxb are clamped to vcm- buf which is initially low. after the pdn bit is released (set to ?0?) the outputs begin to ramp with vcmbuf towards the nominal quiescent voltage. this ramp takes approximately 200 ms to complete. the gradual voltage ramping allows time for t he external dc-blocking capacitors to charge to vcmbuf, effectively blocking the quiescent dc voltage. audio output from the dacs will begin after approximately 2000 sam- ple periods. 4.4.7.2 power-down to prevent audio transients at power-down, the dc-bl ocking capacitors must fully discharge before turn- ing off the power. in order to do this, either the pdn bit should be set or the device should be reset about 250 ms before removing power. during this time, the voltage on vcmbuf and the aoutx outputs dis- charge gradually to gnd. if power is removed before this 250 ms time period has passed, a transient will occur when the va supply drops below that of vc mbuf. there is no minimum time for a power cycle; power may be re-applied at any time. mux ain1a ain2a ain3a ain5a ain4a aoutx_sel[2:0] aoutxa aoutxb dac2a dac1a mux ain1b ain2b ain3b ain5b ain4b dac2b dac1b figure 18. analog output architecture
ds721a6 37 cs42324 4.4.7.3 serial interface clock changes when changing the serial port clock ratio or sample rate, it is recommended that zero data (or near zero data) be present on sdin for at least 10 lrck sa mples before the change is made. during the clocking change, the dac outputs will always be in a zero data state. if non-zero serial audio i nput is present at the time of switching, a slight clic k or pop may be heard as the dac output automatically goes to it?s zero data state. 4.4.8 mute control the mutecx pins become active during power-up initialization, reset, software/hardware muting, and power-down mode (pdn=1). the mutecx pins are intended to be used as control for an external mute circuit in order to add off-chip mute capability. use of the mute control function is not mandator y but recommended for designs requiring the absolute minimum in extraneous clicks an d pops. also, use of the mute c ontrol function can enable the system designer to achieve idle channel noise/signal-to-nois e ratios which are only limited by the external mute circuit. the mutecx pins are active-low cmos drivers. 4.5 initialization the initialization and power-down sequence flow chart is shown in figure 19 on page 39 . the codec en- ters a power-down state upon initial power-up. the in terpolation and decimation filters, delta-sigma modu- lators and software registers are reset. the internal voltage reference, multi-bit dacs and adc, and on-chip amplifiers are powered down. 4.5.1 determining hardwa re or software mode the device will remain in the po wer-down state until the rst pin is brought high. if there is a pull-up on sdout, or sdout is held high by any other means at the time rst pin is brought high, the device will enter hardware mode and begin powering up immediately. if no pull-up is present, or sdout is held low by any other means at the time rst pin is brought high, the device will enter software mode. 4.5.2 hardware mode start-up when the pull-up on sdout is present hardware mo de is selected. once hardware mode is selected, the hardware mode c onfiguration pins are used to set up the device and power-up will occur following the hw startup path as shown in figure 19 on page 39 . the modes of configuration for this mode can be found in section 4.6.1 "hardware mode" on page 40 . because of the lim ited configuration abilities in hard- ware mode, many modes of operation are not available. only mclk1 needs to be applied. once the appropriate mclk1 is valid and rst is high, the quiescent voltage, vcmadc and vcmbuf, and the internal voltage references, filt + and vcm_adc, will begin powering up to normal operation. during this voltage reference ramp delay, both sdout and the aoutxa/aoutxb outputs will be auto matically muted. once lrckx is valid, mclkx occurrences are counted over one lrckx period to determine the mclkx/lrckx frequency ratio and normal operation begins. it is recommended that rst be activated if the analog or digital supplies drop below the recommended operating condition to preven t power-glitch-related issues.
38 ds721a6 cs42324 4.5.2.1 recommended power-up sequence, hardware mode 1. hold rst low until mclk1 and the power supplies are stable. 2. bring rst high (sdout must be pulled high). 3. apply all lrckx, sclkx and sdin signals for normal operation to begin. 4. bring rst low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. 4.5.2.2 recommended power-down sequence, hardware mode to minimize audible pops when turning off or placing the codec in standby: 1. mute the sdin1 and sdin2 streams feeding the codec. 2. bring rst low. 4.5.3 software mode start-up when no pull-up on sdout is present, the software mode is accessible once rst is high. the desired register settings can be loaded per the interface descriptions in ?software mode - i2c control port? on page 41 . when the desired configuration is complete the pdn bit in ?operational control (address 02h)? on page 47 should be set to 0 to initiate the power up sequence. the quiescent voltage, vcmadc and vcmbuf, and the internal voltage references, filt + and vcm_adc, will then begin powering up to nor- mal operation. during this voltage reference ramp delay, both sdout and the aoutxa/aoutxb outputs will be automatically muted. once lrckx is valid, mclkx occurrences are counted over one lrckx pe- riod to determine the mclkx/lrckx frequency ratio and normal operation begins. it is recommended that rst be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues. 4.5.3.1 recommended power-up sequence, software mode 1. hold rst low until the power supplies are stable. 2. bring rst high, the device will be in ?standby?. 3. load the desired register settings while keeping the pdn bit set to ?1?b. 4. start mclk1 (and mclk2 if it is used) to the appropriate frequency, as discussed in section 4.1.1 . 5. set the pdn bit to ?0?b. 6. apply all lrckx, sclkx and sdin signals for normal operation to begin. 7. bring rst low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. 4.5.3.2 recommended power-do wn sequence, software mode to minimize audible pops when turning off or placing the codec in standby: 1. using the appropriate re gisters, 9mute the aoutxa , aoutxb, dac?s & adc?s. 2. set the pdn bit in the power cont rol register to ?1?b. the codec will not power down until it reaches a fully muted sate. 3. bring rst low.
ds721a6 39 cs42324 4.5.4 initialization flow chart figure 19. initializ ation flow chart dac / adc initialization software mode registers setup to desired settings. rst = low? no power 1. no audio signal generated. off mode (power applied) 1. no audio signal generated. 2. control port registers reset to default. pull-up on sdout? hardware mode minimal feature set support. pdn bit = '1'b? sub-clocks applied 1. lrckx valid. 2. sclkx valid. 3. audio samples processed. valid mclkx/lrckx ratio? no yes no yes no yes yes no normal operation audio signal generated per control port or stand- alone settings. analog output freeze 1. aoutx bias = last audio sample. 2. dac modulators stop operation. 3. audible pops. error: mclkx removed pdn bit set to '1'b (software mode only) standby mode 1. no audio signal generated. 2. control port registers retain settings. 3. update control port registers as required. reset transition 1. pops suppressed. power off transition 1. audible pops. error: power removed 20 ms delay charge caps 1. vcmadc/vcmdac charged to quiescent voltage. 2. filt+/vbias charged. 2048 internal mclkx cycle delay digital/analog output muted 20 s delay (dac only) stand-by transition 1. pops suppressed. error: mclkx/lrckx ratio change rst = low power applied
40 ds721a6 cs42324 4.6 device control in software mode, all functions and features may be co ntrolled either by two-wire i2c or spi software mode interface. in hardware mode, a limited feature set may be controlled via hardware control pins. 4.6.1 hardware mode a limited feature-set is available when the cs 42324 powers up in hardware mode (see ?recommended power-up sequence, hardware mode? on page 38 ) and may be controlled via hardware control pins. table 9 shows a list of functions/features, the default co nfiguration and the associated hardware control available. hardware mode feature summary feature/function default configuration hardware control power control adc dac1 dac2 powered up powered up powered up - - - sp_error enabled; active low, open drain - auto detect enabled (256x/128xfs, 512x/256xfs only) - serial port master/slave and speed mode (selectable) ?m0? and ?m1?, pins 1 and 2 (see page 29 ) async / sync mode synchronous only - mclk divide (selectable) ?mdiv? pin 3 (see page 30 ) serial port interface format serial port 1 serial port 2 (selectable) ?dif? pin 5 (see page 32 ) freeze bit settings disabled - adc volume & gain soft ramp zero cross mute invert volume enabled disabled disabled disabled 0 db - - - - - adc high-pass filter adc high-pass filter freeze enabled continuous dc subtraction - - ain input select to adc (sdout source) ain1 - dac1 & dac2 volume & gain soft ramp zero cross mute invert mixer volume enabled disabled disabled disabled disabled (?00?) 0 db - - - - - - dac1 & dac2 de-emphasis disabled - aout1x source output of dac1 - aout2x source output of dac2 - aout3x source ain1x - aoutxx mute (selectable) mute pin 4 (see page 37 ) table 9. hardware mode feature summary
ds721a6 41 cs42324 4.6.2 software mode - i2c control port software mode is used to access the registers, a llowing the cs42324 to be configured for the desired operational modes and formats. the operation in software mode may be completely asynchronous with respect to the audio sample rates. however, to avoi d potential interference problems, the i2c pins should remain static if no operation is re quired. software mode supports the i2c interface, with the cs42324 act- ing as a slave device. sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl. pin ad0 forms the least significant bit of the chip address and shoul d be connected through a resistor to vl or gnd as desired. the state of the pin is sens ed while the cs42324 is being reset. the signal timings for a read and write cycle are shown in figure 20 and figure 21 . a start condition is defined as a falling transition of sda while the clock is high. a stop co ndition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs42324 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 5 bits of the 7-bit address fi eld are fixed at 10011. to communicate with a cs42324, the chip address field, which is the first byte sent to the cs42324, should match 10011 followed by the settings of ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a read, the contents of the register pointe d to by the map will be output. setting the auto increment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs42324 after each input byte is read, and is input to the cs42324 from the microcontroller after each transmitted byte. since the read operation can not set the map, an aborted write operation is used as a preamble. as shown in figure 21 , the write operation is aborted after the acknowledge for the map byte by sending a stop condition. the following pseudocode illustrate s an aborted write operatio n followed by a read oper- ation. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 20. software mode timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 1 0 0 1 1 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 21. software mode timing, i2c read
42 ds721a6 cs42324 send start condition. send 10011xx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10011xx1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto increment bit in the map allows success ive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. 4.6.3 software mode - spi control port in spi mode, data is clocked into the serial control data line, cdin, by the serial clock, cclk (see figure 22 for the clock to data relationship). there are no ad0 or ad1 pins. pin cs is the chip select signal and is used to control spi writes to the registers. when th e device detects a high-to-low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. 4.6.3.1 spi write to write to the device, follow the procedure below while adhering to the softw are mode switching speci- fications in ?switching characteristics - software mode - spi format? section on page 25 . 1. bring cs low. 2. the address byte on the cdin pin must then be 10011110 (r/w =0). 3. write to the memory address pointer, map. th is byte points to the register to be written. 4. write the desired data to the register pointed to by the map. 5. if the incr bit (see section 4.6.4.1 ) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6. if the incr bit is set to 0 and furt her spi writes to other registers are desired, it is necessary to bring cs high, and follow the procedure detailed from step 1. if no further writes to other registers are desired, bring cs high 4.6.3.2 spi read to read from the device, follow the procedure bel ow while adhering to the values specified in ?switching characteristics - software mode - spi format? section on page 25 . 1. bring cs low. 2. the address byte on the cdin pin must then be 10011111 (r/w =1). 3. cdout pin will then output the data from the register pointed to by the map, which is set during the spi write operation. 4. if the incr bit (see section 4.6.4.1 ) is set to 1, keep cs low and continue providing clocks on cclk to read from multiple consecutive registers. bring cs high when reading is complete.
ds721a6 43 cs42324 5. if the incr bit is set to 0 and further spi reads from other registers are desired, it is necessary to bring cs high, and follow the procedure detailed from step 1. if no further reads from other registers are desired, bring cs high. 4.6.4 memory addr ess pointer (map) the map byte comes after the address byte and selects the register to be read or written. refer to the pseudo code above for implementation details. 4.6.4.1 map increment (incr) the device has map auto increment capability enabled by the incr bit (the msb) of the map. if incr is set to 0, map will stay constant for su ccessive i2c writes or reads and spi writes. if incr is set to 1, map will auto increment afte r each byte is written, a llowing block reads or writes of successive registers. 4.7 interrupts and overflow the cs42324 has a comprehensive inte rrupt capability. the in t output pin is intended to drive the interrupt input pin on the host microcontroller. the int pin may fu nction as either an active high cmos driver or an active low open-drain driver (see ?operational control (address 02h)? on page 47 ). when configured as ac- tive low open-drain, the int pin has no active pull-up transistor, allowing it to be used for wired-or hook- ups with multiple peripherals connect ed to the microcontroller interrupt input pin. in this configuration, an external pull-up resistor must be plac ed on the int pin for proper operation. many conditions can cause an interrupt, as listed in the interrupt status register descriptions. see ?interrupt status (address 18h) (read only)? on page 61 . each source may be masked off through mask register bits. in addition, each sour ce may be set to rising ed ge, falling edge, or level sensitive. combined with the option of level sensitive or edge sensitive modes within the mi crocontroller, many different configurations are pos- sible, depending on the needs of th e equipment designer. reading the inte rrupt status register will clear the interrupt condtion. the cs42324 also has a dedicated overflow output. the ovfl pin functions as active low open drain and has no active pull-up transistor, thereby requiring an external pull-up resistor. the ovfl pin outputs an or of the adc overflow positive and negative conditions available in the interrupt status register; however, these conditions do not need to be unmasked for proper operation of the ovfl pin. map msb lsb data byte 1 byte n r/w r/w address chip address chip msb lsb msb lsb map = memory address pointer, 8 bits, msb first high impedance 1001111 1001111 cclk cdin cdout cs figure 22. software mode timing, spi mode
44 ds721a6 cs42324 5. register qu ick reference this table shows the register names and their associated de fault values. all bits marked as ?reserved? must main- tain their default values. addr function 7 65 4 32 1 0 00h device id device3 device2 device1 device0 rev3 rev2 rev1 rev0 page 46 0110 xxxx 01h mute control reserved sys_mclk dac2_ mutel dac2_ muter dac1_ mutel dac1_ muter adc_ mutel adc_ muter page 46 01000000 02h operational control reserved pdn int_hl freeze res erved tri-sdout tri-sp1 tri-sp2 page 47 01000000 03h serial port 1 control sp1_m/s reserved reserved sp1_ speed mclk1 freq1 mclk1 freq0 reserved sp1_mclk page 49 00000000 04h serial port 2 control sp2_m/s reserved reserved sp2_ speed mclk2 freq1 mclk2 freq0 reserved sp2_mclk page 50 00000000 05h reserved reserved reserved reserved reserved reserved reserved reserved reserved 00000000 06h adc clocking reserved adc_ mclk reserved adc_ sp reserved reserved adc_dif1 adc_dif0 page 50 00001000 07h dac1 clocking reserved dac1_ mclk reserved dac1_sp reserved reserved dac1_dif1 dac1_dif0 page 51 00011000 08h dac2 clocking reserved dac2_ mclk reserved dac2_sp reserved reserved dac2_dif1 dac2_dif0 page 52 00011000 09h reserved reserved reserved reserved reserved reserved reserved reserved reserved 00000000 0ah adc control reserved adc_ hpfrz adc_ soft reserved reserved ain_sel2 ain_sel1 ain_sel0 page 52 10100001 0bh dac1 control dac1_ deph dac1_ sngvol dac1_soft dac1_zc dac1_ loopback dac1_inv dac1_mix1 dac1_mix0 page 53 00100000 0ch dac2 control dac2_ deph dac2_ sngvol dac2_ soft dac2_ zc dac2_ loopback dac2_inv dac2_mix1 dac2_mix0 page 55 00100000 0dh aout1 control reserved reserve d reserved reserved mutec1 aout1_ sel2 aout1_ sel1 aout1_ sel0 page 56 00000110 0eh aout2 control reserved reserve d reserved reserved mutec2 aout2_ sel2 aout2_ sel1 aout2_ sel0 page 57 00000111 0fh aout3 control reserved reserve d reserved reserved mutec3 aout3_ sel2 aout3_ sel1 aout3_ sel0 page 57 00000001
ds721a6 45 cs42324 10h adc ch a volume control adca_ vol7 adca_ vol6 adca_ vol5 adca_ vol4 adca_ vol3 adca_ vol2 adca_ vol1 adca_ vol0 page 58 00000000 11h adc ch b volume control adcb_ vol7 adcb_ vol6 adcb_ vol5 adcb_ vol4 adcb_ vol3 adcb_ vol2 adcb_ vol1 adcb_ vol0 page 58 00000000 12h dac1 ch a volume control dac1a_ vol7 dac1a_ vol6 dac1a_ vol5 dac1a_ vol4 dac1a_ vol3 dac1a_ vol2 dac1a_ vol1 dac1a_ vol0 page 58 00000000 13h dac1 ch b volume control dac1b_ vol7 dac1b_ vol6 dac1b_ vol5 dac1b_ vol4 dac1b_ vol3 dac1b_ vol2 dac1b_ vol1 dac1b_ vol0 page 58 00000000 14h dac2 ch a volume control dac2a_ vol7 dac2a_ vol6 dac2a_ vol5 dac2a_ vol4 dac2a_ vol3 dac2a_ vol2 dac2a_ vol1 dac2a_ vol0 page 59 00000000 15h dac2 ch b volume control dac2b_ vol7 dac2b_ vol6 dac2b_ vol5 dac2b_ vol4 dac2b_ vol3 dac2b_ vol2 dac2b_ vol1 dac2b_ vol0 page 59 00000000 16h interrupt mode sp2_ clkerr1 sp2_ clkerr0 sp1_ clkerr1 sp1_ clkerr0 dac_ amute1 dac_ amute0 adc_ ovflx1 adc_ ovflx0 page 59 00000000 17h interrupt mask dac2_ amutelm dac2_ amuterm dac1_ amutelm dac1_ amuterm sp2_ clkerrm sp1_ clkerrm adc_ ovflpm adc_ ovflnm page 59 00000000 18h interrupt status dac2_ amutel dac2_ amuter dac1_ amutel dac1_ amuter sp2_ clkerr sp1_ clkerr adc_ ovflp adc_ ovfln page 61 00000000 addr function 7 65 4 32 1 0
46 ds721a6 cs42324 6. register description all registers are read/write except where otherwise noted. see the following bit definition tables for bit assignment information. the default state of each bi t after release of reset is listed in th e shaded row of each bit description table. when writing to registers containing ?reserved? bits , all bits marked as ?reserved? must maintain their default values. 6.1 device i.d. and revi sion register (address 00h) (read only) 6.1.1 device i.d. (read only) i.d. code for the cs42324. 6.1.2 chip revision (read only) cs42324 revision level. 6.2 mute control (address 01h) 6.2.1 system mclk source this bit selects which mclk pin provides the clock fo r internal state machines. it must always be set to whichever clock is currently active. 6.2.2 mute dac2 left-channel when set, this bit e ngages internal mute circuit on dac2 output. 76543210 device3 device2 device1 device0 rev3 rev2 rev1 rev0 device[3:0] device 0110 cs42324 rev[3:0] revision level 000 a1 001 b0 76543210 reserved sys_mclk dac2_ mutel dac2_ muter dac1_ mutel dac1_ muter adc_ mutel adc_ muter sys_mclk system mclk source 0 mclk1 1 mclk2 dac2_mutel mute status of dac2 left-channel 0 un-muted 1muted
ds721a6 47 cs42324 6.2.3 mute dac2 right-channel when set, this bit engages internal mute circuit on dac2 output. 6.2.4 mute dac1 left-channel when set, this bit engages internal mute circuit on dac1 output. 6.2.5 mute dac1 right-channel when set, this bit engages internal mute circuit on dac1 output. 6.2.6 mute adc left-channel when set, this bit engages internal mute circuit on adc output. 6.2.7 mute adc right-channel when set, this bit engages internal mute circuit on adc output. 6.3 operational control (address 02h) 6.3.1 global power-down when set, this bit places the device in power-down mode. dac2_muter mute status of dac2 right-channel 0 un-muted 1 muted dac1_mutel mute status of dac1 left-channel 0 unmuted 1 muted dac1_muter mute status of dac1 right-channel 0 un-muted 1 muted adc_mutel mute status of adc left-channel 0 un-muted 1 muted adc_muter mute status of adc right-channel 0 un-muted 1 muted 76543210 reserved pdn int_h/l freeze reserved tri-sdout tri-sp1 tri-sp2 pdn device power-down state 0 device is running 1 device is in power-down mode
48 ds721a6 cs42324 6.3.2 int pin high/ low active (int_h/l ) when this bit is set, the int pin will function as an ac tive high cmos driver. when this bit is cleared, the int pin will function as an active low open drain driver a nd will require an external pu ll-up resistor for prop- er operation. 6.3.3 freeze this function allows modifications to be made to cert ain bits without the changes taking effect until the freeze bit is disabled. to make multiple changes to these bits take effect si multaneously, set the freeze bit, make all changes, then clear the freeze bit. the bits affected by the freeze function are listed in table 10 . 6.3.4 tri-state sdout when this bit is set, sdout will be placed in a hi gh-impedance state. 6.3.5 tri-state serial port 1 when enabled, and the device is configured as a ma ster, then sclk1 and lrck1 of serial port 1 (sp1) will be placed in a high-impedance outp ut state. if serial port 1 is configured as a slave, sclk1 and lrck1 will remain as inputs. int_h/l int pin polarity 0 active low, open drain driver 1 active high, cmos driver freeze freeze status 0 changes to registers take effect immediately 1 changes to registers are held until freeze is released name register bit(s) mute control 01h 7:0 adc ch a vol. control 0fh 7:0 adc ch b vol. control 10h 7:0 dac1 ch a vol. control 11h 7:0 dac1 ch b vol. control 12h 7:0 dac2 ch a vol. control 13h 7:0 dac2 ch b vol. control 14h 7:0 table 10. freeze-able bits tri-sdout sdout state 0 output 1 high-impedance tri-sp1 sclk1 and lrck1 state 0 sclk1 and lrck1 operate as inputs if serial port 1 is configured as a slave; sclk1 and lrck1 operate as outputs if serial port 1 is configured as a master 1 sclk1 and lrck1 operate as inputs if serial po rt 1 is configured as a slave; sclk1 and lrck1 become high-impedance outputs if serial port 1 is configured as a master
ds721a6 49 cs42324 6.3.6 tri-state serial port 2 when enabled, and the device is configured as a ma ster, then sclk2 and lrck2 of serial port 2 (sp2) will be placed in a high-impedance output state. if serial port 2 is configured as a slave, sclk2 and lrck2 will remain as inputs. sdin1 and sd in2 are always configured as inputs. 6.4 serial port 1 control (address 03h) 6.4.1 serial port 1 master/slave select this bit configures serial port 1 to operate as either a clock master or clock slave. 6.4.2 serial port 1 speed mode in master mode this bit configures the speed mode of serial port 1. 6.4.3 mclk1 divider these bits configure the internal mclk1 dividers. 6.4.4 serial port 1 mclk source this bit selects which mclk pin provides the clock fo r deriving master mode sub- clocks for serial port 1. tri-sp2 sclk2 and lrck2 state 0 sclk2 and lrck2 operate as inputs if serial po rt 2 is configured as a slave; sclk2 and lrck2 operate as outputs if serial port 2 is configured as a master 1 sclk2 and lrck2 operate as inputs if serial port 2 is configured as a slave; sclk2 and lrck2 become high-impedance outputs if serial port 2 is configured as a master 76543210 sp1_m/s reserved reserved sp1_speed mclk1 freq1 mclk1 freq0 reserved sp1_mclk sp1_m/s serial port 1 master/slave select 0 slave mode 1 master mode sp1_speed serial port 1 speed mode 0 single-speed mode (ssm) 1 double-speed mode (dsm) mclk1 freq[1:0] mclk divider 00 1 01 1.5 10 2 11 3 sp1_mclk serial port 1 mclk source 0 mclk1 1mclk2
50 ds721a6 cs42324 6.5 serial port 2 control (address 04h) 6.5.1 serial port 2 master/slave select this bit configures serial port 2 to operat e as either a clock master or clock slave. 6.5.2 serial port 2 speed mode in master mode this bit configures the speed mode of serial port 2. 6.5.3 mclk2 divider these bits configure the internal mclk2 dividers. 6.5.4 serial port 2 mclk source this bit selects which mclk pin provides the clock for deriving master mode sub-clocks for serial port 2. 6.6 adc clocking (address 06h) 6.6.1 adc mclk source this bit selects which mclk pin provides the clock for the adc. 76543210 sp2_m/s reserved reserved0 sp2_speed mclk2 freq1 mclk2 freq0 reserved sp2_mclk sp2_m/s serial port 2 master/slave select 0 slave mode 1 master mode sp2_speed serial port 2 speed mode 0 single-speed mode (ssm) 1 double-speed mode (dsm) mclk2 freq[1:0] mclk divider 00 1 01 1.5 10 2 11 3 sp2_mclk serial port 2 mclk source 0 mclk1 1mclk2 76543210 reserved adc_mclk reserved adc_sp reserved reserved adc_dif1 adc_dif0 adc_mclk adc mclk source 0 mclk1 1mclk2
ds721a6 51 cs42324 6.6.2 adc serial port source this bit selects which serial port provides the sub clocks for the adc. 6.6.3 adc digital interface format (adc_dif) these bits configure the serial audio interface format for transmitting digital audio data on sdout 6.7 dac1 clocking (address 07h) 6.7.1 dac1 mclk source this bit selects which mclk pin provides the clock for dac1. 6.7.2 dac1 serial port source this bit selects which serial port provides the sub clocks for the dac1. 6.7.3 dac1 digital interf ace format (dac1_dif) these bits configure the serial audio interface format for incoming digital audio data on sdin1. adc_sp adc sub clock source 0 serial port 1 (sclk1/lrck1) 1 serial port 2 (sclk2/lrck2) adc_dif[1:0] adc serial au dio interface format 00 left-justified, 24-bit data 01 i2s, 24-bit data 10 reserved 11 reserved 76543210 reserved dac1_mclk reserved dac1_sp reserved reserved dac1_dif1 dac1_dif0 dac1_mclk dac1 mclk source 0 mclk1 1mclk2 dac1_sp dac1 sub clock source 0 serial port 1 (sclk1/lrck1) 1 serial port 2 (sclk2/lrck2) dac1_dif[1:0] dac1 serial audio interface format 00 left-justified, up to 24-bit data 01 i2s, up to 24-bit data 10 right justified, 16-bit data 11 right justified, 24-bit data
52 ds721a6 cs42324 6.8 dac2 clocking (address 08h) 6.8.1 dac2 mclk source this bit selects which mclk pi n provides the clock for dac2. 6.8.2 dac2 serial port source this bit selects which serial port pr ovides the sub clocks for the dac2. 6.8.3 dac2 digital inte rface format (dac2_dif) these bits configure the serial audio interface format for incoming digital audio data on sdin2. 6.9 adc control (address 0ah) 6.9.1 adc high-pass filter freeze the high-pass filter works by contin uously subtracting a meas ure of the dc offset from the output of the decimation filter. if the adc_hpfrz bit is taken high during normal operation, the current value of the dc offset is frozen and this dc offs et will continue to be subtracted from the conversion result. for dc mea- surements, this bit must be set to ?1?. 6.9.2 adc soft ramp control soft ramp allows level changes, bo th muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the ne w level at a rate of 1 db per 8 left/right clock periods. 76543210 reserved dac2_mclk reserved dac2_sp reserved reserved dac2_dif1 dac2_dif0 dac2_mclk dac2 mclk source 0 mclk1 1mclk2 dac2_sp dac2 sub clock source 0 serial port 1 (sclk1/lrck1) 1 serial port 2 (sclk2/lrck2) dac2_dif[1:0] dac2 serial audio interface format 00 left-justified, up to 24-bit data 01 i2s, up to 24-bit data 10 right justified, 16-bit data 11 right justified, 24-bit data 76543210 reserved adc_hpfrz adc_soft reserved reserved ain_sel2 ain_sel1 ain_sel0 adc_hpfrz adc high-pass filter freeze 0 continuous dc subtraction 1 fixed dc subtraction
ds721a6 53 cs42324 6.9.3 analog input selection these bits are used to select the input source for the adc. 6.10 dac1 control (address 0bh) 6.10.1 dac1 de-emphasis control this bit enables the digital filter to apply the standard 15 s/50 s digital de-emphasis filter response for a sample rate (fs) of 44.1 khz. de-emphasi s is available only in single-speed mode. 6.10.2 dac1 single volume control the individual channel volume levels are independently controlled by their respec tive volume control reg- isters when this function is disabled. when enabled, the volume on dac1 channe ls is determined by the dac1a volume control register and the dac1b volume control register is ignored. 6.10.3 dac1 soft ramp control soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. adc_soft adc soft ramp control 0 off 1on ain_sel[2:0] adc soft ramp control 000 reserved 001 line-level input pair 1 010 line-level input pair 2 011 line-level input pair 3 100 line-level input pair 4 101 line-level input pair 5 110 reserved 111 reserved 76543210 dac1_deph dac1_sngv ol dac1_soft dac1_zc dac1_ loopback dac1_inv dac1_mix1 dac1_mix0 dac1_deph dac1 de-emphasis control 0 off 1 on (valid for fs = 44.1 khz) dac1_sngvol dac1 single volume control 0 off 1on dac1_soft dac1 soft ramp control 0off 1 on
54 ds721a6 cs42324 6.10.4 dac1 zero cross control zero cross enable dictates that signal level changes, either by attenuation chan ges or muting, will occur on a signal zero crossing to minimize audible arti facts. the requested level change will occur after a time- out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp and zero cross enable soft ramp and zero cross enable dictate that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and be implemented on a signal zero crossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sam- ple rate) if the signal does not encounter a zero cr ossing. the zero cross function is independently mon- itored and implemented for each channel. 6.10.5 dac1 loop-back loops adc sdout, sclk, and lrck to dac1 serial port pins. 6.10.6 dac1 invert signal polarity when enabled, this bit will effect a 180 de gree phase shift in the dac1 channels. 6.10.7 dac1 channel mixer these bits implement mono mixes of the left and ri ght channels as well as a left/right channel swap. dac1_soft dac1_zc mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled dac1_loop_ back dac1 loop-back 0 off 1 on dac1_inv dac1 invert signal polarity 0 off 1 on dac1_mix[1:0] dac1 outa dac1 outb 00 l r 01 10 11 r l lr + 2 ---------- - lr + 2 ---------- -
ds721a6 55 cs42324 6.11 dac2 control (address 0ch) 6.11.1 dac2 de-emphasis control this bit enables the digital filter to apply the standard 15 s/50 s digital de-emphasis filter response for a sample rate (fs) of 44.1 khz. de-emphasi s is available only in single-speed mode. 6.11.2 dac2 single volume control the individual channel volume levels are independently controlled by their respec tive volume control reg- isters when this function is disabled. when enabled, the volume on dac2 channe ls is determined by the dac2a volume control register and the dac2b volume control register is ignored. 6.11.3 dac2 soft ramp control soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. 6.11.4 dac2 zero cross control zero cross enable dict ates that signal level cha nges, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a time- out period between 512 and 1024 sample periods (10. 7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp and zero cross enable soft ramp and zero cross enable dictate that signal le vel changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and be implemented on a signal zero crossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sam- ple rate) if the signal does not encounter a zero crossing. the zero cross f unction is independently mon- itored and implemented for each channel. 76543210 dac2_deph dac2_ sngvol dac2_soft dac2_zc dac2_ loop_back dac2_inv dac2_mix1 dac2_mix0 dac2_deph dac2 de-emphasis control 0 off 1 on (valid for fs = 44.1 khz) dac2_sngvol dac2 single volume control 0 off 1on dac2_soft dac2 soft ramp control 0off 1 on dac2_soft dac2_zc mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled
56 ds721a6 cs42324 6.11.5 dac2 loop-back loops adc sdout, sclk, and lrck to dac1 serial port pins. 6.11.6 dac2 invert signal polarity when enabled, this bit will effect a 180 de gree phase shift in the dac2 channels. 6.11.7 dac2 channel mixer these bits implements mono mixes of the left and right channels as well as a left/right channel swap. 6.12 aout1 control (address 0dh) 6.12.1 external mute control pin this bit controls the logic st ate of the corresponding mutec1 pin. though this bit is active high, it should be noted that the mutec1 pin is active low. 6.12.2 aout1 select these bits are used to select the analog output source. dac2_loop_ back dac2 loop-back 0 off 1 on dac2_inv dac2 invert signal polarity 0 off 1 on dac2_mix[1:0] dac2 outa dac2 outb 00 l r 01 10 11 r l 76543210 reserved reserved reserved reserved mu tec1 aout1_sel2 aout1_sel1 aout1_sel0 mutec1 output on mutec1 pin 0 high (mute disengaged) 1 low (mute engaged) aout1_sel[2:0] aout1 source 000 reserved 001 ain pair 1 010 ain pair 2 011 ain pair 3 100 ain pair 4 101 ain pair 5 110 dac1 output pair 111 dac2 output pair lr + 2 ---------- - lr + 2 ---------- -
ds721a6 57 cs42324 6.13 aout2 control (address 0eh) 6.13.1 external mute control pin this bit controls the logic state of the corresponding mutec2 pin. though this bit is active high, it should be noted that the mutec2 pin is active low. 6.13.2 aout2 select these bits are used to select the analog output source. 6.14 aout3 control (address 0fh) 6.14.1 external mute control pin this bit controls the logic state of the corresponding mutec3 pin. though this bit is active high, it should be noted that the mutec3 pin is active low. 76543210 reserved reserved reserved reserved mutec2 aout2_sel2 aout2_sel1 aout2_sel0 mutec2 output on mutec2 pin 0 high (mute disengaged) 1 low (mute engaged) aout2_sel[2:0] aout2 source 000 reserved 001 ain pair 1 010 ain pair 2 011 ain pair 3 100 ain pair 4 101 ain pair 5 110 dac1 output pair 111 dac2 output pair 76543210 reserved reserved reserved reserved mutec3 aout3_sel2 aout3_sel1 aout3_sel0 mutec3 output on mutec3 pin 0 high (mute disengaged) 1 low (mute engaged)
58 ds721a6 cs42324 6.14.2 aout3 select these bits are used to select the analog output source. 6.15 adcx volume control: adca (address 10h) & adcb (address 11h) the level for each channel of the adc can be adjusted in 0.5 db increments as dictated by the adc soft and zero cross bits (adc_soft) from +12 to -84 db . levels are decoded in tw o?s complement, as shown in the table below. 6.16 dac1x volume control: dac1a (address 12h) & da c1b (address 13h) the level for each channel of dac1 output can be adj usted in 0.5 db increments as dictated by the dac1 soft and zero cross bits (dac1_soft & dac1_zc) from 0 to -127.5 db. levels are decoded as unsigned, as shown in the table below. aout3_sel[2:0] aout3 source 000 reserved 001 ain pair 1 010 ain pair 2 011 ain pair 3 100 ain pair 4 101 ain pair 5 110 dac1 output pair 111 dac2 output pair 76543210 adcx_vol7 adcx_vol6 adcx_vol5 adcx_vol4 adcx_vol3 adcx_vol2 adcx_vol1 adcx_vol0 binary code volume setting 0001 1000 +12.0 db 0000 0000 0.0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0101 1000 -84.0 db all other values reserved 76543210 dac1x_vol7 dac1x_vol6 dac1x_vol5 dac1x_vol4 dac1x_vol3 dac1x_vol2 dac1x_vol1 dac1x_vol0 binary code volume setting 0000 0000 0 db 0000 0001 -0.5 db 0000 0010 -1.0 db 1111 1111 -127.5 db
ds721a6 59 cs42324 6.17 dac2x volume control: dac1a (address 14h) & dac1b (address 15h) the level for each channel of dac2 output can be ad justed in 0.5 db increments as dictated by the dac2 soft and zero cross bits (dac2_soft & dac2_zc) from 0 to -127.5 db. levels are decoded in unsigned, as shown in the table below. 6.18 interrupt mode (address 16h) the interrupt mode register contains four two-bit codes which correspond to either an interrupt status bit or group of bits as shown below. there are three ways to set the int pin active in accordance with the interrupt condition. in the rising-edge active mode, the int pin becomes active on the arrival of the interrupt condi- tion. in the falling-edge active mode , the int pin becomes active on the removal of the in terrupt condition. in level active mode, the int pin remains active during the interrupt condition . 6.19 interrupt mask (address 17h) these bits are mask bits for the corresponding bits in the ?interrupt status (address 18h) (read only)? reg- ister on page 61 . 76543210 dac2x_vol7 dac2x_vol6 dac2x_vol5 dac2x_vol4 dac2x_vol3 dac2x_vol2 dac2x_vol1 dac2x_vol0 binary code volume setting 0000 0000 0 db 0000 0001 -0.5 db 0000 0010 -1.0 db 1111 1111 - 127.5 db 76543210 sp2_ clkerr1 sp2_ clkerr0 sp1_ clkerr1 sp1_ clkerr0 dac_amute1 dac_amute0 adc_ ovflx1 adc_ ovflx0 interrupt mode associated interrupt status bit(s) sp2_clkerr[1:0] sp2_clkerr sp1_clkerr[1:0] sp1_clkerr dac_amute[1:0] dac2_amutel, dac2_a muter, dac1_amutel, dac1_amuter adc_avflx[1:0] adc_ovflp, adc_ovfln bit settings interrupt mode setting 00 rising-edge active 01 falling-edge active 10 level active 11 reserved 76543210 dac2_ amutelm dac2_ amuterm dac1_ amutelm dac1_ amuterm sp2_ clkerrm sp1_ clkerrm adc_ ovflpm adc_ ovflnm bit settings bit in interrupt register 0 not masked 1 masked
60 ds721a6 cs42324 6.19.1 dac2 auto mute left mask (dac2_amutelm) this bit serves as a mask for the dac2 auto mute left interrupt source. if this bit is cleared, the dac2_amutel interrupt is unmasked, meaning that if the dac2_amutel condition occurs, the int pin will go active according to the dac_amute[1:0] bits in the ?interrupt mode (address 16h)? register on page 59 . if the dac2_amutelm bit is set, the dac2_amu tel condition is masked, meaning that its oc- currence will not affect the int pin. 6.19.2 dac2 auto mute ri ght mask (dac2_amuterm) this bit serves as a mask for the dac2 auto mute left interrupt source. if this bit is cleared, the dac2_amuter interrupt is unmasked, meaning that if the dac2_amuter condition occurs, the int pin will go active according to the dac_amute[1:0] bits in the ?interrupt mode (address 16h)? register on page 59 . if the dac2_amuterm bit is set, the dac2_amu ter condition is masked, meaning that its occurrence will not affect the int pin. 6.19.3 dac1 auto mute left mask (dac1_amutelm) this bit serves as a mask for the dac1 auto mute left interrupt source. if this bit is cleared, the dac1_amutel interrupt is unmasked, meaning that if the dac1_amutel condition occurs, the int pin will go active according to the dac_amute[1:0] bits in the ?interrupt mode (address 16h)? register on page 59 . if the dac1_amutelm bit is set, the dac1_amu tel condition is masked, meaning that its oc- currence will not affect the int pin. 6.19.4 dac1 auto mute ri ght mask (dac1_amutelm) this bit serves as a mask for the dac1 auto mute left interrupt source. if this bit is cleared, the dac1_amuter interrupt is unmasked, meaning that if the dac1_amuter condition occurs, the int pin will go active according to the dac_amute[1:0] bits in the ?interrupt mode (address 16h)? register on page 59 . if the dac1_amuterm bit is set, the dac1_amu ter condition is masked, meaning that its occurrence will not affect the int pin. 6.19.5 serial port 2 clock error mask (sp2_clkerrm) this bit serves as a mask for the serial port 2 clock error interrupt source. if this bit is cleared, the sp2_clkerr interrupt is un masked, meaning that if the sp2_clkerr bit is set, the int pin will go ac- tive according to the sp2_c lkerr[1:0] bits in the ?interrupt mode (address 16h)? register on page 59 . if the sp2_clkerrm bit is set, the sp2_clkerr condition is masked, meaning that its occurrence will not affect the int pin. 6.19.6 serial port 1 clock error mask (sp1_clkerrm) this bit serves as a mask for the serial port 1 clock error interrupt source. if this bit is cleared, the sp1_clkerr interrupt is un masked, meaning that if the sp1_clkerr bit is set, the int pin will go ac- tive according to the sp1_c lkerr[1:0] bits in the ?interrupt mode (address 16h)? register on page 59 . if the sp1_clkerrm bit is set, the sp1_clkerr condition is masked, meaning that its occurrence will not affect the int pin.
ds721a6 61 cs42324 6.19.7 adc positive over flow mask (adc_ovflpm) this bit serves as a mask for the adc positive over flow interrupt source. if th is bit is cleared, the adc_ovflp interrupt is un masked, meaning that if the adc_ovfl p conditions are met in the interrupt status register, the int pin will go active a ccording to the adc_ovflx[1:0] bits in the ?interrupt mode (ad- dress 16h)? register on page 59 . if the adc_ovflpm bit is set, the adc_ovflp condition is masked, meaning that its occurrenc e will not affect the int pin. however, the ovfl pin will continue to reflect the overflow state of the adc. 6.19.8 adc negative overfl ow mask (adc_ovflnm) this bit serves as a mask for the adc negative over flow interrupt source. if this bit is cleared, the adc_ovfln interrupt is unmasked, meaning that if the adc_ovfln co nditions are met in the interrupt status register, the int pin will go active a ccording to the adc_ovflx[1:0] bits in the ?interrupt mode (ad- dress 16h)? register on page 59 . if the adc_ovflnm bit is set, the adc_ovfln condition is masked, meaning that its occurrenc e will not affect the int pin. however, the ovfl pin will continue to reflect the overflow state of the adc. 6.20 interrupt status (address 18h) (read only) this register defaults to 00h and is read only. if the in t pin is active, reading this register clears the interrupt condition. 6.20.1 dac2 auto mute left interrupt status (dac2_amutel) this bit is read only. when set, in dicates that dac2 left channel has had an auto-mute condition since the last read of this register. condit ions which cause an auto-mute, such as receiving 4096 consecutive sam- ples of zeroes or ones on the left channel of sdin2, will cause this bit to be set. this in terrupt status bit is an edge-triggered event and will be cleared following a read of this register. the int pin will go active according to the dac_amute[1:0] bits in the ?interrupt mode (address 16h)? on page 59 and the status of this bit if dac2_amutelm bit is cleared. 6.20.2 dac2 auto mute right interrupt status (dac2_amuter) this bit is read only. when set, indicates that dac2 right channel has had an auto-mute condition since the last read of this register. conditions which c ause an auto-mute, such as receiving 4096 consecutive samples of zeroes or ones on the ri ght channel of sdin2, will cause this bit to be set. this interrupt status bit is an edge-triggered even t and will be cleared following a read of this register. the int pin will go active according to the dac_amute[1:0] bits in the ?interrupt mode (address 16h)? on page 59 and the status of this bit if dac2_amuterm bit is cleared. 76543210 dac2_ amutel dac2_ amuter dac1_ amutel dac1_ amuter sp2_ clkerr sp1_ clkerr adc_ ovflp adc_ ovfln bit settings bit in interrupt register 0 interrupt has not occurred since the last read of this register. 1 interrupt has occurred since the last read of this register.
62 ds721a6 cs42324 6.20.3 dac1 auto mute left in terrupt status (dac1_amutel) this bit is read only. when set, indicates that dac1 left channel has had an auto-mute condition since the last read of this register. conditions which cause an auto-mute, such as receiv ing 4096 consecutive sam- ples of zeroes or ones on the left ch annel of sdin1, will cause this bit to be set. this inte rrupt status bit is an edge-triggered event and will be cleared following a read of this register. the int pin will go active according to the dac_amute[1:0] bits in the ?interrupt mode (address 16h)? on page 59 and the status of this bit if dac1_amutelm bit is cleared. 6.20.4 dac1 auto mute right in terrupt status (dac1_amutel) this bit is read only. when set, indicates that da c1 right channel has had an auto-mute condition since the last read of this register. conditions which cause an auto-mute, such as receiving 4096 consecutive samples of zeroes or ones on the righ t channel of sdin1, will cause this bi t to be set. this interrupt status bit is an edge-triggered even t and will be cleared following a read of this register. the int pin will go active according to the dac_amute[1:0] bits in the ?interrupt mode (address 16h)? on page 59 and the status of this bit if dac1_amuterm bit is cleared. 6.20.5 serial port 2 clock error interrupt status (sp2_clkerr) this bit is read only. when set, in dicates that serial port 2 has had a clock error since the last read of this register. conditions which cause a clock error in th e serial port, such as loss of lrck2, sclk2, an mclkx/lrck2 ratio change, or speed mode change, will cause this bit to be set. this in terrupt bit is an edge-triggered event and will be cleared following a read of this register. the int pin will go active according to the sp2_clkerr[1:0] bits in the ?interrupt mode (address 16h)? on page 59 and the status of this bit if sp2_clkerrm bit is cleared. 6.20.6 serial port 1 clock error interrupt status (sp1_clkerr) this bit is read only. when set, in dicates that serial port 1 has had a clock error since the last read of this register. conditions which cause a clock error in th e serial port, such as loss of lrck1, sclk1, an mclkx/lrck1 ratio change, or speed mode change, will cause this bit to be set. this in terrupt bit is an edge-triggered event and will be cleared following a read of this register. the int pin will go active according to the sp1_clkerr[1:0] bits in the ?interrupt mode (address 16h)? on page 59 and the status of this bit if sp1_clkerrm bit is cleared. 6.20.7 adc positive overflow interrupt bit (adc_ovflp) this bit is read only. when set, indicates that a pos itive over-range condition occurred anywhere in the cs42324 adc signal path and has adc data has been c lipped to positive full scal e since the last read of this register. this in terrupt bit is an ed ge-triggered event and will be clear ed following a read of this reg- ister. the int pin will go active according to the adc_ovflx[1:0] bits in the ?interrupt mode (address 16h)? on page 59 and the status of this bit if adc_ovflpm bit is cleared. to determine t he current overflow state of the adc use the ovfl pin.
ds721a6 63 cs42324 6.20.8 adc negative overflow interrupt bit (adc_ovfln) this bit is read only. when set, indicates that a ne gative over-range condition occurred anywhere in the cs42324 adc signal path and has adc data has been clipped to negative full scale since the last read of this register. this interrupt bit is an edge-trig gered event and will be cleared following a read of this register. the int pin will go active according to t he adc_ovflx[1:0] bits in the ?interrupt mode (address 16h)? on page 59 and the status of this bit if adc_ovflnm bit is cleared. to determine the current overflow state of the adc use the ovfl pin.
64 ds721a6 cs42324 7. grounding and powe r supply decoupling as with any high-resolution converter, the cs42324 requires careful attention to power supply and grounding ar- rangements if its potential perf ormance is to be realized. figure 7 on page 26 shows the recommended power ar- rangements, with va connected to a clean supply. vd, which powers the digital filter, may be run from the system logic supply (vl) or may be powered from the analog supply (va) via a resistor. in this case, no additional devices should be powered from vd. power supply decoupling capacitors should be as near to the cs42324 as possible, wit h the low value ceramic ca- pacitor being the nearest. all signals, especially clocks , should be kept away from the filt+, vcm_adc, vbias, vcmbuf, and vcmdac pins in order to avoid unwanted coupling into the modulators. the filt+, vcm_adc, vbias, vcmbuf, and vcmdac deco upling capacitors, particularly the 0.1 f, must be positioned to minimize the electrical path from each pin to gnd. the cs42324 ev aluation board demonstrates the optimum layout and power supply arrangements. to minimize digital noise, conne ct the cs42324 digital outputs only to cmos inputs.
ds721a6 65 cs42324 8. adc filter plots figure 23. single-speed mode stopband rejection figure 24. single-speed mode transition band -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 25. single-speed mode transition band (d etail) figure 26. single-speed mode passband ripple -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db) figure 27. double-speed mode stopband rejectio n figure 28. double-speed mode transition band -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db)
66 ds721a6 cs42324 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 29. double-speed mode transition band (d etail) figure 30. double-speed mode passband ripple
ds721a6 67 cs42324 9. dac digital filter resp onse plots 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 31. single-speed stopband rejectio n figure 32. single-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 33. single-speed transition band (det ail) figure 34. single-speed passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 35. double-speed stopband rejection figure 36. double-speed transition band
68 ds721a6 cs42324 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 37. double-speed transition band (det ail) figure 38. double-speed passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 39. quad-speed stopband rejection figure 40. quad-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 41. quad-speed transition band (detail) figure 42. quad-speed passband ripple
ds721a6 69 cs42324 10.parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the spec ified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement technique has been accept ed by the audio engineer ing society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right chan nels. measured for each channel at the converter's output with no signal to the input under test and a full-sc ale signal applied to the ot her channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale an alog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
70 ds721a6 cs42324 11.package dimensions thermal characteristics and specifications inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm *controlling di mension is mm. *jedec designation: ms022 parameters symbol min typ max units package thermal resistance multi-layer dual-layer ja ja jc - - - 48 65 15 - - - c/watt c/watt c/watt 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
ds721a6 71 cs42324 12.ordering information 13.revision history product description package pb-free grade temp range container order # cs42324 2-in, 4-out audio codec with 2vrms analog i/o lqfp yes commercial -40c to +85 c tray CS42324-CQZ cs42324 2-in, 4-out audio codec with 2vrms analog i/o lqfp yes automotive -40c to +105 c tray cs42324-dqz cdb42324 evaluation board - - - - cdb42324 release changes a5 changed title a6 corrected scl/cclk pin description (pin 2) in the pin description table on page 8 . contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc . and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limit ation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (?critical applications?). cirr us products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclusion of cirrus products in such applic ations is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, incl uding the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its offi cers, directors, employ ees, distributors and other agents from any and all liability, includ- ing attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and pro duct names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola, inc.

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